Meudon, France (Paris) Training Center
Service Formation
Immeuble Le Pasteur
13 / 15 rue Jeanne Braconnier
Meudon, France
33 1-40-94-74-74
33 1-46-01-91-75
View Map
Classes
| Course Title | Next Date | Category | ||||||
|---|---|---|---|---|---|---|---|---|
|
Capital Harness XC
This course introduces you to the basic and more complex functionality within the Capital Harness XC product. This tool provides a seamless transition of data from Capital Logic or Integrator into Capital Harness XC. More upcoming dates (1 total)
|
5/22/13 | Capital | ||||||
|
DxDesigner for Expedition PCB Flow
This course will help you to improve your knowledge and skills with Design Definition solutions. More upcoming dates (3 total)
|
6/4/13 | DxDesigner, Expedition | ||||||
|
OVM to UVM Transition
This course is for engineers who are familiar with the Open Verification Methodology (OVM) and would like to learn testbench development with the Universal Verification Methodology (UVM). Covered are the new and changed features of UVM from OVM. More upcoming dates (1 total)
|
6/5/13 | HDL & Other Languages, SystemVerilog | ||||||
|
Expedition PCB Introduction
Expedition® PCB Introduction presents the workflow and methods of laying out a printed circuit board using the latest version of Mentor Graphics Expedition PCB. From fundamental library concepts, to the PCB editor environment and the PCB layout process, you will gain hands-on experience in integrating a source schematic, placing and routing the board, and outputting the fabrication data. More upcoming dates (3 total)
|
6/10/13 | Expedition | ||||||
|
ModelSim / Questa Core: Advanced Topics
ModelSim® / Questa® Core: Advanced Topics teaches you to capitalize on the extensive capabilities of ModelSim / Questa Core to effectively and efficiently analyze and debug digital HDL designs. Using various ModelSim / Questa Core features and techniques, you will learn how to produce higher performance test benches, more reliable device-under-test models, and greater confidence of simulation thoroughness and completeness. More upcoming dates (1 total)
|
6/18/13 | Questa & ModelSim | ||||||
|
ModelSim / Questa Core: HDL Simulation
ModelSim / Questa Core: HDL Simulation teaches you to effectively use ModelSim / Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how ModelSim / Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow. Hands-on lab exercises will reinforce lecture and discussion topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors. More upcoming dates (1 total)
|
6/20/13 | FPGA, HDL & Other Languages, Questa & ModelSim | ||||||
|
CES for Expedition PCB
This Course covers all the necessary skills required to use CES efficiently and effectively in DxDesigner-Expedition flow. More upcoming dates (3 total)
|
6/25/13 | Expedition | ||||||
|
CES for Board Station XE Flow
This course is designed to cover all the necessary skills required to use CES efficiently and effectively in Board Station XE design flow. More upcoming dates (1 total)
|
6/27/13 | Board Station | ||||||
|
FloEFD for Creo
This course is designed to provide new users of FloEFD Creo with a background sufficient for tackling a wide range of flow and thermal analysis problems. The main goals of the course are to make the student familiar with the operation and functionality of FloEFD Creo and to instill good engineering modeling practices. More upcoming dates (2 total)
|
7/9/13 | FloEFD | ||||||
|
FloTHERM
This course will teach you how to use the FloTHERM thermal analysis software. Complete with instruction and tutorial exercises, the training guides you through all aspects of model building, using SmartParts and libraries, importing data from MCAD and EDA software, sequential optimization and visualization of results. More upcoming dates (2 total)
|
7/9/13 | FloTHERM | ||||||
|
Tessent MemoryBIST and LogicBIST
This course will help you understand how to implement DFT for memory and logic test. You will be introduced to Tessent™ technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow. The lecture/lab format of the class gives you a conceptual understanding of how BIST circuitry for random logic and memories can be automatically generated and inserted into a circuit. More upcoming dates (1 total)
|
9/3/13 | Tessent | ||||||
|
SystemVerilog Universal Verification Methodology
This 4-day course is for engineers who are interested in developing SystemVerilog verification environments using the Universal Verification Methodology (UVM). More upcoming dates (1 total)
|
9/24/13 | HDL & Other Languages, SystemVerilog | ||||||
|
Expedition PCB Flow: Automation and Scripting
This course will help you understand how you can customize the PCB flow tools, DxDesigner® and Expedition, to both integrate the tools into your process flows as well as enhance their capabilities. More upcoming dates (1 total)
|
10/2/13 | Expedition | ||||||
|
Thermal Management of Electronic Systems
The objective of this course is to provide designers with an understanding of the principles and practice of thermal management. More upcoming dates (1 total)
|
10/15/13 | FloEFD, FloTHERM, FloVENT |
Recommended accommodations
Please mention the Mentor Graphics Training Center when booking your hotel accommodations, as we frequently negotiate special rates for students.
Contact us
Mentor Graphics Education Services
1-800-345-2308
Email Us