Bangalore, India Training Center
Salarpuria Touchstone
Sy. No15/1A block & 14, Third Floor
Kadubeesanahally, Varthur Hobli
Bangalore, India
+91-80-3051-4000
+91-80-3051-4004
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Classes
| Course Title | Next Date | Category | ||
|---|---|---|---|---|
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Calibre Fundamentals: Writing DRC/LVS Rules
This course will teach you to effectively write and maintain Calibre nmDRC and nmLVS rule decks for your semiconductor processes. In this class, you will extensively study the Standard Verification Rule Format (SVRF) language used in Calibre rule decks. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. Hands-on lab exercises will reinforce lecture topics and provide you with rule writing experience under the guidance of our industry expert instructors. More upcoming dates (1 total)
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6/18/13 | Calibre | ||
|
SystemVerilog for Verification
This intensive, practical course is intended for Verification Engineers interested in the latest verification enhancements to SystemVerilog. While many engineers may have extensive verification experience this course will introduce best-practice usage of SystemVerilog features like Object Oriented programming, Constrained Randomization and Functional Coverage. More upcoming dates (1 total)
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7/23/13 | HDL & Other Languages, SystemVerilog | ||
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SystemVerilog Universal Verification Methodology
This 4-day course is for engineers who are interested in developing SystemVerilog verification environments using the Universal Verification Methodology (UVM). More upcoming dates (1 total)
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10/22/13 | HDL & Other Languages, SystemVerilog | ||
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SystemVerilog Universal Verification Methodology Advanced
This course is for engineers with experience in developing SystemVerilog verification environments using the Universal Verification Methodology (UVM). More upcoming dates (1 total)
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11/27/13 | HDL & Other Languages, SystemVerilog | ||
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OVM to UVM Transition
This course is for engineers who are familiar with the Open Verification Methodology (OVM) and would like to learn testbench development with the Universal Verification Methodology (UVM). Covered are the new and changed features of UVM from OVM. More upcoming dates (1 total)
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12/2/13 | HDL & Other Languages, SystemVerilog |
Recommended accommodations
Please mention the Mentor Graphics Training Center when booking your hotel accommodations, as we frequently negotiate special rates for students.
Contact us
Mentor Graphics Education Services
1-800-345-2308
Email Us