Herzliya, Israel Training Center
10 Aba Eban Street,
Building C
PO Box 2155
Herzliya, Israel
972-9-9718655
972-9-9552627
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Classes
| Course Title | Next Date | Category | ||||||
|---|---|---|---|---|---|---|---|---|
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SystemVerilog Universal Verification Methodology
This 4-day course is for engineers who are interested in developing SystemVerilog verification environments using the Universal Verification Methodology (UVM). More upcoming dates (2 total)
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5/19/13 | HDL & Other Languages, SystemVerilog | ||||||
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ReqTracer for FPGA/ASIC Design Assurance
This course will help students learn how to automate the tracing of design requirements to design and test data associated with an FPGA or ASIC design. This class is targeted at engineers and technical managers tasked with carrying out design assurance activities needed to certify for customers or regulatory agencies that the device performs its intended function. More upcoming dates (1 total)
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5/21/13 | FPGA | ||||||
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Thermal Management of Electronic Systems
The objective of this course is to provide designers with an understanding of the principles and practice of thermal management. More upcoming dates (1 total)
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5/27/13 | FloEFD, FloTHERM, FloVENT | ||||||
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Calibre Fundamentals: Performing DRC/LVS
Learn how to leverage the full power of Calibre nmDRC and Calibre nmLVS by attending the ‘Calibre Fundamentals: Performing DRC/LVS’ course. This course will teach you to effectively use Mentor Graphics Calibre nmDRDC and Calibre LVS software in your layout verification flow and will empower you to analyze DRC and LVS results successfully in coordination with a layout editor. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre nmDRC and Calibre nmLVS toolset. More upcoming dates (1 total)
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5/29/13 | Calibre | ||||||
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Tessent Scan and ATPG
This course teaches you how to insert full scan in a design using the DFTAdvisor™ tool flow, and shows you how to create high quality test patterns using the ATPG tool flow. This course also teaches you ATPG compression techniques along with industry-standard Tessent TestKompress compression techniques. More upcoming dates (3 total)
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6/3/13 | Tessent | ||||||
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HDL Designer Series
This class teaches you to use HDL Designer Series effectively in your FPGA or ASIC design process. The lecture takes you through the HDL Designer Series design flow. This includes modeling the design with both graphics and text, generating HDL, and then simulating and animating the design to verify behavior. More upcoming dates (2 total)
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6/10/13 | FPGA, HDL & Other Languages | ||||||
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Tessent MemoryBIST
This course will help you understand how to implement DFT for memory test. You will be introduced to Tessent™ technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow. The lecture/lab format of the class gives you a conceptual understanding of how BIST circuitry for random logic and memories can be automatically generated and inserted into a circuit. More upcoming dates (1 total)
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6/16/13 | Tessent | ||||||
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HyperLynx Power Integrity Analysis
This course will help you understand the basic concepts of power distribution and delivery on a PCB, power integrity simulation, identification of power distribution problems on your PCB, and fixing these problems early in the design cycle. More upcoming dates (1 total)
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6/24/13 | Expedition, HyperLynx, PADS | ||||||
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SystemVerilog for Verification
This intensive, practical course is intended for Verification Engineers interested in the latest verification enhancements to SystemVerilog. While many engineers may have extensive verification experience this course will introduce best-practice usage of SystemVerilog features like Object Oriented programming, Constrained Randomization and Functional Coverage. More upcoming dates (1 total)
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7/7/13 | HDL & Other Languages, SystemVerilog | ||||||
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CES for Expedition PCB
This Course covers all the necessary skills required to use CES efficiently and effectively in DxDesigner-Expedition flow. More upcoming dates (1 total)
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7/15/13 | Expedition | ||||||
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ModelSim / Questa Core: Advanced Topics
ModelSim® / Questa® Core: Advanced Topics teaches you to capitalize on the extensive capabilities of ModelSim / Questa Core to effectively and efficiently analyze and debug digital HDL designs. Using various ModelSim / Questa Core features and techniques, you will learn how to produce higher performance test benches, more reliable device-under-test models, and greater confidence of simulation thoroughness and completeness. More upcoming dates (1 total)
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7/23/13 | Questa & ModelSim | ||||||
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HyperLynx Advanced High-Speed PCB Analysis
This course will help you understand the application of HyperLynx SI to solve real world signal integrity problems. It covers two design areas in both pre- and post-layout: source-synchronous design analysis and SERDES design analysis More upcoming dates (1 total)
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7/29/13 | Expedition, HyperLynx, PADS | ||||||
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Calibre Advanced Topics: Mastering Calibre eqDRC
Calibre® eqDRC represents an important breakthrough in physical verification, making it possible for anyone performing design rule and LVS checks to truly do more with less. More upcoming dates (1 total)
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8/4/13 | Calibre | ||||||
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Calibre Fundamentals: DESIGNrev
This course will teach you to analyze, compare, and manipulate layout data using Calibre DESIGNrev, Calibre’s state-of-the-art layout viewer. More upcoming dates (1 total)
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8/27/13 | Calibre | ||||||
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OVM to UVM Transition
This course is for engineers who are familiar with the Open Verification Methodology (OVM) and would like to learn testbench development with the Universal Verification Methodology (UVM). Covered are the new and changed features of UVM from OVM. More upcoming dates (1 total)
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9/15/13 | HDL & Other Languages, SystemVerilog | ||||||
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Tessent TestKompress and Advanced Topics
This course introduces Embedded Deterministic Test (EDT™) technology and Tessent™ TestKompress® to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with smaller (< 130 nm) geometries. It is especially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size or application time are issues. More upcoming dates (1 total)
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9/30/13 | Tessent | ||||||
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Calibre Fundamentals: Writing DRC/LVS Rules
This course will teach you to effectively write and maintain Calibre nmDRC and nmLVS rule decks for your semiconductor processes. In this class, you will extensively study the Standard Verification Rule Format (SVRF) language used in Calibre rule decks. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. Hands-on lab exercises will reinforce lecture topics and provide you with rule writing experience under the guidance of our industry expert instructors. More upcoming dates (1 total)
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10/6/13 | Calibre | ||||||
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Expedition PCB Advanced
This course will help you understand many of the advanced layout options available for Expedition PCB, including many of the purchasable utilities. More upcoming dates (1 total)
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10/14/13 | Expedition | ||||||
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ModelSim / Questa Core: HDL Simulation
ModelSim / Questa Core: HDL Simulation teaches you to effectively use ModelSim / Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how ModelSim / Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow. Hands-on lab exercises will reinforce lecture and discussion topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors. More upcoming dates (1 total)
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11/5/13 | FPGA, HDL & Other Languages, Questa & ModelSim | ||||||
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Questa Essentials
This course will teach you the benefits of Questa’s advanced verification environment. Lectures include advanced functional verification topics such as constrained-random stimulus generation, functional coverage, code coverage, and SystemVerilog assertions. More upcoming dates (1 total)
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11/18/13 | Questa & ModelSim | ||||||
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PSL: Assertion Based Verification with Questa
This class introduces you to the concept of Assertion Based Verification (ABV), and gives you the tools to start using the techniques in your design and verification tasks. The class introduces the PSL language, Accellera Version 1.1, so that you can write the properties and assertions for your code, and also considers simulating with the assertions using Questa and its assertion capabilities. It shows how Questa's assertion capabilities combine with its other aspects to help you debug your design efficiently. You will also be introduced to the Assertion Thread Viewer, and its use in debugging assertion issues. More upcoming dates (1 total)
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12/9/13 | HDL & Other Languages, Questa & ModelSim | ||||||
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Calibre Advanced Topics: nmLVS Debug Case Studies
Layout Versus Schematic (LVS) verification has always played a critical role in the IC design process. Calibre nmLVS continues to be the pre-eminent tool for this task. Recent Calibre enhancements have significantly extended the tool’s capabilities and have helped to streamline the LVS debugging task. This course will introduce you to all of these new features through a series of LVS case studies. More upcoming dates (1 total)
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12/17/13 | Calibre |
Recommended accommodations
Please mention the Mentor Graphics Training Center when booking your hotel accommodations, as we frequently negotiate special rates for students.
Contact us
Mentor Graphics Education Services
1-800-345-2308
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