Milan, Italy Training Center
Piazza Montanelli 20
02 24 98 94.1
02 24 98 94 200
|Course Title||Next Date||Category|
SystemVerilog for Verification
This intensive, practical course is intended for Verification Engineers interested in the latest verification enhancements to SystemVerilog. While many engineers may have extensive verification experience this course will introduce best-practice usage of SystemVerilog features like Object Oriented programming, Constrained Randomization and Functional Coverage.
More upcoming dates (1 total)
|10/21/14||HDL & Other Languages, SystemVerilog|
Please mention the Mentor Graphics Training Center when booking your hotel accommodations, as we frequently negotiate special rates for students.