Online Training
Many Mentor Graphics training courses are available as Live Online classes, a great alternative when a local class does not suit your requirements.
| Course Title | Next Date | Category | ||||||
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PADS Layout
This course will teach you the workflow of laying out a printed circuit board using the latest version of Mentor Graphics PADS Layout. You will be guided through the steps necessary to design a printed circuit board. Course highlights include creating physical components, importing netlists, adding/updating parts, routing connections, generating reports and Gerber information. More upcoming dates (2 total)
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5/23/13 | PADS | ||||||
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FloTHERM
This course will teach you how to use the FloTHERM thermal analysis software. Complete with instruction and tutorial exercises, the training guides you through all aspects of model building, using SmartParts and libraries, importing data from MCAD and EDA software, sequential optimization and visualization of results. More upcoming dates (3 total)
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5/29/13 | FloTHERM | ||||||
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DxDesigner for Expedition PCB Flow
This course will help you to improve your knowledge and skills with Design Definition solutions. More upcoming dates (2 total)
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5/29/13 | DxDesigner, Expedition | ||||||
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Calibre Fundamentals: Performing DRC/LVS
Learn how to leverage the full power of Calibre nmDRC and Calibre nmLVS by attending the ‘Calibre Fundamentals: Performing DRC/LVS’ course. This course will teach you to effectively use Mentor Graphics Calibre nmDRDC and Calibre LVS software in your layout verification flow and will empower you to analyze DRC and LVS results successfully in coordination with a layout editor. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre nmDRC and Calibre nmLVS toolset. More upcoming dates (1 total)
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5/29/13 | Calibre | ||||||
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Capital Logic Interactive
This course was developed to provide a detailed look at the capital logic toolset, taking the participant from the basic through to the more complex wiring designs. More upcoming dates (1 total)
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5/29/13 | Capital | ||||||
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Expedition PCB for Design Review
The Expedition® PCB for Design Review course will help design engineers learn a few basic features of Expedition PCB so they can conduct a successful design review. More upcoming dates (1 total)
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5/30/13 | Expedition | ||||||
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Tessent Scan and ATPG
This course teaches you how to insert full scan in a design using the DFTAdvisor™ tool flow, and shows you how to create high quality test patterns using the ATPG tool flow. This course also teaches you ATPG compression techniques along with industry-standard Tessent TestKompress compression techniques. More upcoming dates (2 total)
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6/3/13 | Tessent | ||||||
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AMPLE
During this course you will acquire the skills needed to customize Falcon Framework based applications (Board Station, Design Architect, IC Station) and efficiently utilize them according to your specific company needs and requirements. Under the guidance of our industry expert instructors, create new functions and tools for use in your applications thereby automating time consuming and repetitive manual tasks. More upcoming dates (1 total)
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6/3/13 | Board Station | ||||||
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PADS Logic and Layout
The PADS Logic and Layout on-demand course teaches you the workflow of designing a printed circuit board using Mentor Graphics PADS Logic and PADS Layout. Course content and labs are available for 30 days from first login. More upcoming dates (1 total)
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6/3/13 | PADS | ||||||
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DxDesigner for Design Capture Users
This course will help you to improve your knowledge and skills with Design Definition solutions. More upcoming dates (3 total)
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6/3/13 | DxDesigner | ||||||
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PSL: Assertion Based Verification with Questa
This class introduces you to the concept of Assertion Based Verification (ABV), and gives you the tools to start using the techniques in your design and verification tasks. The class introduces the PSL language, Accellera Version 1.1, so that you can write the properties and assertions for your code, and also considers simulating with the assertions using Questa and its assertion capabilities. It shows how Questa's assertion capabilities combine with its other aspects to help you debug your design efficiently. You will also be introduced to the Assertion Thread Viewer, and its use in debugging assertion issues. More upcoming dates (1 total)
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6/3/13 | HDL & Other Languages, Questa & ModelSim | ||||||
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Library Manager for DxDesigner to Expedition PCB Flow
This course will give you the skills necessary to create, protect, add to and change the different data types in your Central Library. The lecture modules discuss the Central Library philosophy as well as how to use the Library Manager tools and how to best interface library objects into your design process. More upcoming dates (2 total)
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6/4/13 | DxDesigner, Expedition | ||||||
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SystemVerilog Universal Verification Methodology
This 4-day course is for engineers who are interested in developing SystemVerilog verification environments using the Universal Verification Methodology (UVM). More upcoming dates (3 total)
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6/4/13 | HDL & Other Languages, SystemVerilog | ||||||
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Expedition PCB Introduction
Expedition® PCB Introduction presents the workflow and methods of laying out a printed circuit board using the latest version of Mentor Graphics Expedition PCB. From fundamental library concepts, to the PCB editor environment and the PCB layout process, you will gain hands-on experience in integrating a source schematic, placing and routing the board, and outputting the fabrication data. More upcoming dates (2 total)
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6/10/13 | Expedition | ||||||
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PADS Logic
This course teaches you the workflow of creating a schematic design using the latest version of Mentor Graphics PADS® Logic. You will be guided through the steps necessary to capture schematics. More upcoming dates (3 total)
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6/11/13 | PADS | ||||||
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Calibre Advanced Topics: nmLVS Debug Case Studies
Layout Versus Schematic (LVS) verification has always played a critical role in the IC design process. Calibre nmLVS continues to be the pre-eminent tool for this task. Recent Calibre enhancements have significantly extended the tool’s capabilities and have helped to streamline the LVS debugging task. This course will introduce you to all of these new features through a series of LVS case studies. More upcoming dates (1 total)
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6/11/13 | Calibre | ||||||
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HyperLynx Power Integrity Analysis
This course will help you understand the basic concepts of power distribution and delivery on a PCB, power integrity simulation, identification of power distribution problems on your PCB, and fixing these problems early in the design cycle. More upcoming dates (1 total)
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6/11/13 | Expedition, HyperLynx, PADS | ||||||
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HyperLynx Advanced High-Speed PCB Analysis
This course will help you understand the application of HyperLynx SI to solve real world signal integrity problems. It covers two design areas in both pre- and post-layout: source-synchronous design analysis and SERDES design analysis More upcoming dates (1 total)
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6/17/13 | Expedition, HyperLynx, PADS | ||||||
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SystemVerilog for Verification
This intensive, practical course is intended for Verification Engineers interested in the latest verification enhancements to SystemVerilog. While many engineers may have extensive verification experience this course will introduce best-practice usage of SystemVerilog features like Object Oriented programming, Constrained Randomization and Functional Coverage. More upcoming dates (1 total)
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6/18/13 | HDL & Other Languages, SystemVerilog | ||||||
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ModelSim / Questa Core: Advanced Topics
ModelSim® / Questa® Core: Advanced Topics teaches you to capitalize on the extensive capabilities of ModelSim / Questa Core to effectively and efficiently analyze and debug digital HDL designs. Using various ModelSim / Questa Core features and techniques, you will learn how to produce higher performance test benches, more reliable device-under-test models, and greater confidence of simulation thoroughness and completeness. More upcoming dates (2 total)
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6/18/13 | Questa & ModelSim | ||||||
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CES for Expedition PCB
This Course covers all the necessary skills required to use CES efficiently and effectively in DxDesigner-Expedition flow. More upcoming dates (2 total)
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6/18/13 | Expedition | ||||||
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HyperLynx Signal Integrity Analysis
This course will help you understand basic signal integrity, crosstalk, EMI concepts and pre-and post layout stages of the design process. More upcoming dates (2 total)
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6/19/13 | Expedition, HyperLynx, PADS | ||||||
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ModelSim / Questa Core: HDL Simulation
ModelSim / Questa Core: HDL Simulation teaches you to effectively use ModelSim / Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how ModelSim / Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow. Hands-on lab exercises will reinforce lecture and discussion topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors. More upcoming dates (1 total)
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6/20/13 | FPGA, HDL & Other Languages, Questa & ModelSim | ||||||
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DxDesigner for PADS Flow
Using the DxDesigner tools suite, you will gain proficiency in project management with Dashboard, schematic capture with DxDesigner, part selection using DxDataBook™, and much more. You will also learn how to prepare your final schematic for interfacing with the Mentor Graphics® PADS® Layout tool. More upcoming dates (1 total)
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6/25/13 | DxDesigner, PADS | ||||||
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Expedition PCB Advanced
This course will help you understand many of the advanced layout options available for Expedition PCB, including many of the purchasable utilities. More upcoming dates (2 total)
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6/25/13 | Expedition | ||||||
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I/O Designer
This course teaches you how to manage the data and monitor the changes between the two design flows while maintaining consistency. More upcoming dates (2 total)
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6/25/13 | Expedition, PADS | ||||||
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Calibre DESIGNrev Scripting
This class teaches students how to create custom Calibre DRV scripts and batch files that can be used to analyze and manipulate layout data. This class also teaches students how to extend the Calibre DRV GUI to obtain user input, display results from running DRV scripts, and add menus and menu items to invoke the scripts they write in class. The course presents a number of practical examples that demonstrate how DRV scripting can be leveraged to improve the chip design process. More upcoming dates (1 total)
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7/9/13 | Calibre | ||||||
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Calibre Advanced Topics: Double Patterning
Starting with the 20nm processing node, the use of two masks to print a single layer becomes a requirement because of lithography issues. This course will help you understand the impact of double patterning on your designs and how to use Calibre to find and fix layout problems associated with this approach. More upcoming dates (2 total)
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7/11/13 | Calibre | ||||||
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SystemVerilog Open Verification Methodology
This course is for engineers who are interested in developing SystemVerilog verification environments using the Open Verification Methodology (OVM). More upcoming dates (2 total)
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7/15/13 | HDL & Other Languages, SystemVerilog | ||||||
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PADS Layout Advanced
The PADS Advanced Layout course will help you understand advanced PCB design techniques for the use in printed circuited design. More upcoming dates (3 total)
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7/23/13 | PADS | ||||||
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Tessent Diagnosis
Tessent Diagnosis will teach you to capitalize on the methods of defect discovery on failing devices in a production environment. Using the defect reports from YieldAssist you will be able to plan the analysis process in determining the root cause of failure, reducing time and improving your hit rate. With the correlation between the 'Logical netlist' and the Physical layout you will have a indication of the most likely area where to begin the failure analysis. More upcoming dates (1 total)
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8/19/13 | Tessent | ||||||
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RF Design in DxD/Expedition
This course will help you efficiently implement RF and mixed technology RF designs on an Expedition PCB. In addition, it will teach the process of moving the data back and forth between a DXD/Expedition environment and Microwave office and Agilent ADS tools. More upcoming dates (2 total)
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8/27/13 | DxDesigner, Expedition | ||||||
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SystemVerilog Assertions
This course serves either as an add-on to Mentor graphics’ SystemVerilog for Verification course or as a stand-alone one day class for those with experience in SystemVerilog who wish to become proficient using SystemVerilog Assertions (SVA) for assertion based verification. More upcoming dates (1 total)
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11/11/13 | HDL & Other Languages, SystemVerilog |
On Demand Courses
| Course Title | Next Date | Category |
|---|---|---|
| PADS Logic and Layout The PADS Logic and Layout course teaches you the workflow of designing a printed circuit board using Mentor Graphics PADS Logic and PADS Layout. You are guided through the steps necessary to capture a schematic and design a printed circuit board. Course highlights include creating part types, generating and importing netlists, placing parts, routing connections, generating reports and generating Gerber outputs and interfacing between the two products. | On demand | PADS |
System Requirements for Online Training
Mentor Graphics offers the convenience of on-line learning with the interactivity and depth of a traditional classroom setting. The entire instructor-led course is live and online on your own computer. Labs are included and can be completed between live instructor sessions. The number of class days varies depending on the course. Typically, the student receives four or five hours with the instructor, followed by independent lab exercises. You will need:
- Internet connection with broadband speed or better
- Web browser
- Windows OS
- Ability to install and connect to Webex session
- Ability to conference call
- Ability to run MGC application environment either locally or via our virtual machine
Recommended minimum system requirements for installing temporary training software and license:
- Operating system: Windows XP, Windows 2000, or Windows server 2003
- RAM: 2GB
- Video Card: 64MB
- Processor: Intel Pentium 3 900MHz Minimum, Intel Pentium 4 2+GHz recommended (any modern processor will be fine)
- Disk Space: 12GB available
- 3rd Party Software: Winzip or a similar compression utility
- Local administrator privileges on your computer
Requirements may vary by course. You will be informed of exact requirements upon class confirmation.
Instructors are available by phone for any questions during the lab time.
Contact us
Mentor Graphics Education Services
1-800-345-2308
Email Us