Singapore Training Center

Calibre® eqDRC represents an important breakthrough in physical verification, making it possible for anyone performing design rule and LVS checks to truly do more with less.

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6/24/13

Singapore, SG

This course will help you understand how you can customize the PCB flow tools, DxDesigner® and Expedition, to both integrate the tools into your process flows as well as enhance their capabilities.

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7/01/13

Singapore, SG

HyperLynx 3D Analysis course will help you gain the ability to accurately model and simulate discontinuities such as vias in PCBs in HyperLynx 3D EM environment.

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7/04/13

Singapore, SG

This course will help you understand many of the advanced layout options available for Expedition PCB, including many of the purchasable utilities.

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7/15/13

Singapore, SG

The Expedition Advanced Packaging Bndl enables 3D Advanced packaging design in Expedition. This includes IC packaging, MCM/Hybrid Design and Mixed signal SiP design. 3D Wire bonding, Chip Stacking, substrate cavities as well as integral embedded passives are supported in this flow and are covered in this class.

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8/05/13

Singapore, SG

This course will help you to improve your knowledge and skills with Design Definition solutions.

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8/14/13

Singapore, SG

This course will help you acquire the skills necessary to create and analyze a computational model of a data center while using FloVENT software

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8/26/13

Singapore, SG

IC Design Flow With Pyxis will provide all the knowledge needed to apply the power of Pyxis, Mentor’s integrated IC design environment, to your most challenging VLSI designs. The course covers the full IC design flow, from capture through final layout verification and analysis.

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8/26/13

Singapore, SG

Well-maintained and consistent libraries are the keys to efficient design work in Expedition PCB. The "Library Manager for Expedition PCB" course will give you the skills necessary to create, protect, add to and change the different data types in your Central Library. The lecture modules discuss the Central Library philosophy as well as how to use the Library manager tools and how to best interface library objects into your design process.

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8/26/13

Singapore, SG

Tessent Diagnosis will teach you to capitalize on the methods of defect discovery on failing devices in a production environment. Using the defect reports from YieldAssist you will be able to plan the analysis process in determining the root cause of  failure, reducing time and improving your hit rate. With the correlation between the 'Logical netlist' and the Physical layout you will have a indication of the most likely area where to begin the failure analysis.

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9/09/13

Singapore, SG

This course teaches you how to insert full scan in a design using the DFTAdvisor™ tool flow, and shows you how to create high quality test patterns using the ATPG tool flow. This course also teaches you ATPG compression techniques along with industry-standard Tessent TestKompress compression techniques.

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9/10/13

Singapore, SG

This intensive, practical course is intended for Verification Engineers interested in the latest verification enhancements to SystemVerilog. While many engineers may have extensive verification experience this course will introduce best-practice usage of SystemVerilog features like Object Oriented programming, Constrained Randomization and Functional Coverage.

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9/10/13

Singapore, SG

This 4-day course is for engineers who are interested in developing SystemVerilog verification environments using the Universal Verification Methodology (UVM).

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9/10/13

Singapore, SG

This course is for engineers with experience in developing SystemVerilog verification environments using the Universal Verification Methodology (UVM).

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9/16/13

Singapore, SG

This course is for engineers who are familiar with the Open Verification Methodology (OVM) and would like to learn testbench development with the Universal Verification Methodology (UVM). Covered are the new and changed features of UVM from OVM.

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9/16/13

Singapore, SG

This course introduces Embedded Deterministic Test (EDT™) technology and Tessent™ TestKompress® to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with smaller (< 130 nm) geometries. It is especially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size or application time are issues.

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9/19/13

Singapore, SG

This course will help you understand basic signal integrity, crosstalk, EMI concepts and pre-and post layout stages of the design process.

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9/30/13

Singapore, SG

This course will help you understand the application of HyperLynx SI to solve real world signal integrity problems. It covers two design areas in both pre- and post-layout: source-synchronous design analysis and SERDES design analysis

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10/02/13

Singapore, SG

Learn the methodology, techniques and processes that have enabled the world's foremost electronic design companies to pioneer leading edge designs. Signal integrity and high-speed methodology will teach you to make quality digital designs and printed circuit boards through knowledge of signal integrity.

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10/07/13

Singapore, SG