HsinChu City, Taiwan Training Center
11F, No. 120, Sec. 2, Gongdao 5th Road,
Hsinchu City, Taiwan
886 3 513 1000
886 3 573 4734
View Map
Classes
| Course Title | Next Date | Category | ||
|---|---|---|---|---|
|
Calibre Fundamentals: Writing DRC/LVS Rules
This course will teach you to effectively write and maintain Calibre nmDRC and nmLVS rule decks for your semiconductor processes. In this class, you will extensively study the Standard Verification Rule Format (SVRF) language used in Calibre rule decks. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. Hands-on lab exercises will reinforce lecture topics and provide you with rule writing experience under the guidance of our industry expert instructors. More upcoming dates (1 total)
|
5/21/13 | Calibre | ||
|
Calibre Advanced Topics: Writing PERC Rules
This course will help you understand the wide breadth of problem areas addressed by Calibre PERC, including ESD, advanced ERC, multiple power domains, point-to-point resistance, and current density. More upcoming dates (1 total)
|
5/30/13 | Calibre | ||
|
Tessent Scan and ATPG
This course teaches you how to insert full scan in a design using the DFTAdvisor™ tool flow, and shows you how to create high quality test patterns using the ATPG tool flow. This course also teaches you ATPG compression techniques along with industry-standard Tessent TestKompress compression techniques. More upcoming dates (1 total)
|
6/4/13 | Tessent | ||
|
Tessent TestKompress and Advanced Topics
This course introduces Embedded Deterministic Test (EDT™) technology and Tessent™ TestKompress® to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with smaller (< 130 nm) geometries. It is especially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size or application time are issues. More upcoming dates (1 total)
|
6/6/13 | Tessent | ||
|
Tessent MemoryBIST
This course will help you understand how to implement DFT for memory test. You will be introduced to Tessent™ technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow. The lecture/lab format of the class gives you a conceptual understanding of how BIST circuitry for random logic and memories can be automatically generated and inserted into a circuit. More upcoming dates (1 total)
|
6/12/13 | Tessent | ||
|
Calibre TVF
This course will help you unleash the powers of TVF to make your SVRF files more compact, easier to maintain, and more powerful. Using several examples, you will learn how to incorporate TVF functionality into your rule files to make writing SVRF rules easier. More upcoming dates (1 total)
|
7/11/13 | Calibre | ||
|
Calibre xRC Parasitic Extraction
This course presents the most in-depth coverage of these topics available, extending your knowledge base far beyond existing documentation. Attendees should see immediate ROI in terms of both ramp-up time with the Calibre xRC tools and effectiveness. More upcoming dates (1 total)
|
7/18/13 | Calibre | ||
|
HyperLynx Signal Integrity Analysis
This course will help you understand basic signal integrity, crosstalk, EMI concepts and pre-and post layout stages of the design process. More upcoming dates (1 total)
|
7/24/13 | Expedition, HyperLynx, PADS |
Recommended accommodations
Please mention the Mentor Graphics Training Center when booking your hotel accommodations, as we frequently negotiate special rates for students.
Contact us
Mentor Graphics Education Services
1-800-345-2308
Email Us