Austin, TX Training Center

This class teaches students how to create custom Calibre DRV scripts and batch files that can be used to analyze and manipulate layout data. This class also teaches students how to extend the Calibre DRV GUI to obtain user input, display results from running DRV scripts, and add menus and menu items to invoke the scripts they write in class. The course presents a number of practical examples that demonstrate how DRV scripting can be leveraged to improve the chip design process.

More upcoming dates (1 total)

7/09/13

Austin, TX

Starting with the 20nm processing node, the use of two masks to print a single layer becomes a requirement because of lithography issues. This course will help you understand the impact of double patterning on your designs and how to use Calibre to find and fix layout problems associated with this approach.

More upcoming dates (1 total)

7/11/13

Austin, TX

This course teaches you how to insert full scan in a design using the DFTAdvisor™ tool flow, and shows you how to create high quality test patterns using the ATPG tool flow. This course also teaches you ATPG compression techniques along with industry-standard Tessent TestKompress compression techniques.

More upcoming dates (2 total)

7/16/13	Austin, TX
10/15/13	Austin, TX

This course introduces Embedded Deterministic Test (EDT™) technology and Tessent™ TestKompress® to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with smaller (< 130 nm) geometries. It is especially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size or application time are issues.

More upcoming dates (2 total)

8/20/13	Austin, TX
11/12/13	Austin, TX

This course will teach you how to use the FloTHERM thermal analysis software. Complete with instruction and tutorial exercises, the training guides you through all aspects of model building, using SmartParts and libraries, importing data from MCAD and EDA software, sequential optimization and visualization of results.

More upcoming dates (1 total)

10/22/13

Austin, TX

This course is for engineers who are familiar with the Open Verification Methodology (OVM) and would like to learn testbench development with the Universal Verification Methodology (UVM). Covered are the new and changed features of UVM from OVM.

More upcoming dates (1 total)

1/07/14

Austin, TX

This course is for engineers with experience in developing SystemVerilog verification environments using the Universal Verification Methodology (UVM).

More upcoming dates (1 total)

1/29/14

Austin, TX