Fremont, CA (San Francisco) Training Center

This course is designed to provide new users of FloEFD with a background sufficient for tackling a wide range of flow and thermal analysis problems. The main goals of the course are to make the student familiar with the operation and functionality of FloEFD and to instill good engineering modeling practices.

More upcoming dates (2 total)

6/04/13	Fremont, CA
12/03/13	Fremont, CA

Learn how to leverage the full power of Calibre nmDRC and Calibre nmLVS by attending the ‘Calibre Fundamentals: Performing DRC/LVS’ course. This course will teach you to effectively use Mentor Graphics Calibre nmDRDC and Calibre LVS software in your layout verification flow and will empower you to analyze DRC and LVS results successfully in coordination with a layout editor. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre nmDRC and Calibre nmLVS toolset.

More upcoming dates (2 total)

6/04/13	Fremont, CA
12/10/13	Fremont, CA

This course teaches you how to insert full scan in a design using the DFTAdvisor™ tool flow, and shows you how to create high quality test patterns using the ATPG tool flow. This course also teaches you ATPG compression techniques along with industry-standard Tessent TestKompress compression techniques.

More upcoming dates (1 total)

6/11/13

Fremont, CA

This course will teach you how to use the FloTHERM thermal analysis software. Complete with instruction and tutorial exercises, the training guides you through all aspects of model building, using SmartParts and libraries, importing data from MCAD and EDA software, sequential optimization and visualization of results.

More upcoming dates (5 total)

6/11/13	Fremont, CA
7/16/13	Fremont, CA
8/13/13	Fremont, CA
9/10/13	Fremont, CA
10/15/13	Fremont, CA

This intensive, practical course is intended for Verification Engineers interested in the latest verification enhancements to SystemVerilog. While many engineers may have extensive verification experience this course will introduce best-practice usage of SystemVerilog features like Object Oriented programming, Constrained Randomization and Functional Coverage.

More upcoming dates (3 total)

6/18/13	Fremont, CA
9/24/13	Fremont, CA
2/18/14	Fremont, CA

This course will help you understand many of the advanced layout options available for Expedition PCB, including many of the purchasable utilities.

More upcoming dates (2 total)

6/25/13	Fremont, CA
1/14/14	Fremont, CA

This course will help you understand how you can customize the PCB flow tools, DxDesigner® and Expedition, to both integrate the tools into your process flows as well as enhance their capabilities.

More upcoming dates (1 total)

7/09/13

Fremont, CA

This course is for engineers who are familiar with the Open Verification Methodology (OVM) and would like to learn testbench development with the Universal Verification Methodology (UVM). Covered are the new and changed features of UVM from OVM.

More upcoming dates (2 total)

7/15/13	Fremont, CA
11/21/13	Fremont, CA

This course will teach you to effectively write and maintain Calibre nmDRC and nmLVS rule decks for your semiconductor processes. In this class, you will extensively study the Standard Verification Rule Format (SVRF) language used in Calibre rule decks. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. Hands-on lab exercises will reinforce lecture topics and provide you with rule writing experience under the guidance of our industry expert instructors.

More upcoming dates (2 total)

7/16/13	Fremont, CA
1/14/14	Fremont, CA

This course will help you understand how to implement DFT for memory and logic test. You will be introduced to Tessent™ technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow. The lecture/lab format of the class gives you a conceptual understanding of how BIST circuitry for random logic and memories can be automatically generated and inserted into a circuit.

More upcoming dates (2 total)

7/22/13	Fremont, CA
10/28/13	Fremont, CA

This course is designed to provide new users of FloEFD Creo with a background sufficient for tackling a wide range of flow and thermal analysis problems. The main goals of the course are to make the student familiar with the operation and functionality of FloEFD Creo and to instill good engineering modeling practices.

More upcoming dates (1 total)

7/23/13

Fremont, CA

This course introduces Embedded Deterministic Test (EDT™) technology and Tessent™ TestKompress® to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with smaller (< 130 nm) geometries. It is especially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size or application time are issues.

More upcoming dates (2 total)

7/25/13	Fremont, CA
10/31/13	Fremont, CA

This course teaches you the workflow of creating a schematic design using the latest version of Mentor Graphics PADS® Logic. You will be guided through the steps necessary to capture schematics.

More upcoming dates (3 total)

7/29/13	Fremont, CA
10/22/13	Fremont, CA
1/28/14	Fremont, CA

Using the DxDesigner tools suite, you will gain proficiency in project management with Dashboard, schematic capture with DxDesigner, part selection using DxDataBook™, and much more. You will also learn how to prepare your final schematic for interfacing with the Mentor Graphics® PADS® Layout tool.

More upcoming dates (2 total)

7/29/13	Fremont, CA
1/21/14	Fremont, CA

This course will teach you the workflow of laying out a printed circuit board using the latest version of Mentor Graphics PADS Layout. You will be guided through the steps necessary to design a printed circuit board. Course highlights include creating physical components, importing netlists, adding/updating parts, routing connections, generating reports and Gerber information.

More upcoming dates (3 total)

7/30/13	Fremont, CA
10/23/13	Fremont, CA
1/29/14	Fremont, CA

This course presents the most in-depth coverage of these topics available, extending your knowledge base far beyond existing documentation. Attendees should see immediate ROI in terms of both ramp-up time with the Calibre xRC tools and effectiveness.

More upcoming dates (1 total)

8/05/13

Fremont, CA

This course will help you unleash the powers of TVF to make your SVRF files more compact, easier to maintain, and more powerful. Using several examples, you will learn how to incorporate TVF functionality into your rule files to make writing SVRF rules easier.

More upcoming dates (1 total)

8/07/13

Fremont, CA

This course will give you the skills necessary to create, protect, add to and change the different data types in your Central Library. The lecture modules discuss the Central Library philosophy as well as how to use the Library Manager tools and how to best interface library objects into your design process.

More upcoming dates (1 total)

8/12/13

Fremont, CA

This course will help you to improve your knowledge and skills with Design Definition solutions.

More upcoming dates (2 total)

8/12/13	Fremont, CA
12/09/13	Fremont, CA

This Course covers all the necessary skills required to use CES efficiently and effectively in DxDesigner-Expedition flow.

More upcoming dates (1 total)

8/15/13

Fremont, CA

Expedition® PCB Introduction presents the workflow and methods of laying out a printed circuit board using the latest version of Mentor Graphics Expedition PCB. From fundamental library concepts, to the PCB editor environment and the PCB layout process, you will gain hands-on experience in integrating a source schematic, placing and routing the board, and outputting the fabrication data.

More upcoming dates (1 total)

8/19/13

Fremont, CA

Learn the methodology, techniques and processes that have enabled the world's foremost electronic design companies to pioneer leading edge designs. Signal integrity and high-speed methodology will teach you to make quality digital designs and printed circuit boards through knowledge of signal integrity.

More upcoming dates (1 total)

8/20/13

Fremont, CA

This course covers the Valor NPI operations for incorporating Design for Manufacturing (DFM) analysis into your PCB design process. At the conclusion of this course the attendee will understand the navigation of the Valor NPI system, general tool usage, and analysis review. Focus will be placed on a “Best Practices” process flow that will guide the user through the stages of ODB++ export and EDA input, through analysis and resolution, and finishing with output and reporting.

More upcoming dates (1 total)

9/10/13

Fremont, CA

LP Wizard is a complete set of tools for building and managing your CAD library and documentation. LP Wizard is the only CAD library generation tool officially approved by IPC to match the IPC-7351B standard. The course will familiarize you with the LP Wizard interface and footprint creation.

More upcoming dates (1 total)

9/13/13

Fremont, CA

This course is for engineers who are interested in developing SystemVerilog verification environments using the Open Verification Methodology (OVM).

More upcoming dates (1 total)

9/17/13

Fremont, CA

ModelSim / Questa Core: HDL Simulation teaches you to effectively use ModelSim / Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how ModelSim / Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow. Hands-on lab exercises will reinforce lecture and discussion topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors.

More upcoming dates (1 total)

9/17/13

Fremont, CA

ModelSim® / Questa® Core: Advanced Topics teaches you to capitalize on the extensive capabilities of ModelSim / Questa Core to effectively and efficiently analyze and debug digital HDL designs. Using various ModelSim / Questa Core features and techniques, you will learn how to produce higher performance test benches, more reliable device-under-test models, and greater confidence of simulation thoroughness and completeness.

More upcoming dates (1 total)

9/18/13

Fremont, CA

IC Design Flow With Pyxis will provide all the knowledge needed to apply the power of Pyxis, Mentor’s integrated IC design environment, to your most challenging VLSI designs. The course covers the full IC design flow, from capture through final layout verification and analysis.

More upcoming dates (1 total)

9/24/13

Fremont, CA

This 4-day course is for engineers who are interested in developing SystemVerilog verification environments using the Universal Verification Methodology (UVM).

More upcoming dates (1 total)

10/08/13

Fremont, CA

The PADS Advanced Layout course will help you understand advanced PCB design techniques for the use in printed circuited design.

More upcoming dates (1 total)

10/08/13

Fremont, CA

Starting with the 20nm processing node, the use of two masks to print a single layer becomes a requirement because of lithography issues. This course will help you understand the impact of double patterning on your designs and how to use Calibre to find and fix layout problems associated with this approach.

More upcoming dates (2 total)

10/22/13	Fremont, CA
2/03/14	Fremont, CA

Calibre Fundamentals: DFM Case Studies introduces you to the state-of-the-art tools and processes required for success when designing deep sub-micron integrated circuits.

More upcoming dates (1 total)

10/24/13

Fremont, CA

This course will help you understand basic signal integrity, crosstalk, EMI concepts and pre-and post layout stages of the design process.

More upcoming dates (1 total)

11/05/13

Fremont, CA

This course will help you understand the basic concepts of power distribution and delivery on a PCB, power integrity simulation, identification of power distribution problems on your PCB, and fixing these problems early in the design cycle.

More upcoming dates (1 total)

11/07/13

Fremont, CA

This course is for engineers with experience in developing SystemVerilog verification environments using the Universal Verification Methodology (UVM).

More upcoming dates (1 total)

11/18/13

Fremont, CA

This class teaches students how to create custom Calibre DRV scripts and batch files that can be used to analyze and manipulate layout data. This class also teaches students how to extend the Calibre DRV GUI to obtain user input, display results from running DRV scripts, and add menus and menu items to invoke the scripts they write in class. The course presents a number of practical examples that demonstrate how DRV scripting can be leveraged to improve the chip design process.

More upcoming dates (1 total)

1/27/14

Fremont, CA

Calibre® eqDRC represents an important breakthrough in physical verification, making it possible for anyone performing design rule and LVS checks to truly do more with less.

More upcoming dates (1 total)

2/05/14

Fremont, CA