Training & Services
Mentor Graphics Training
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SystemVerilog for Verification
This intensive, practical course is intended for Verification Engineers interested in the latest verification enhancements to SystemVerilog. While many engineers may have extensive verification experience this course will introduce best-practice usage of SystemVerilog features like Object Oriented programming, Constrained Randomization and Functional Coverage. More upcoming dates (10 total)
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6/18/13 | Dallas, TX | ||||||||||||||||||||
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ModelSim / Questa Core: Advanced Topics
ModelSim® / Questa® Core: Advanced Topics teaches you to capitalize on the extensive capabilities of ModelSim / Questa Core to effectively and efficiently analyze and debug digital HDL designs. Using various ModelSim / Questa Core features and techniques, you will learn how to produce higher performance test benches, more reliable device-under-test models, and greater confidence of simulation thoroughness and completeness. More upcoming dates (6 total)
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6/18/13 | Meudon, FR | ||||||||||||||||||||
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Calibre Fundamentals: Writing DRC/LVS Rules
This course will teach you to effectively write and maintain Calibre nmDRC and nmLVS rule decks for your semiconductor processes. In this class, you will extensively study the Standard Verification Rule Format (SVRF) language used in Calibre rule decks. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. Hands-on lab exercises will reinforce lecture topics and provide you with rule writing experience under the guidance of our industry expert instructors. More upcoming dates (9 total)
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6/18/13 | Bangalore, IN | ||||||||||||||||||||
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CES for Expedition PCB
This Course covers all the necessary skills required to use CES efficiently and effectively in DxDesigner-Expedition flow. More upcoming dates (10 total)
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6/18/13 | Wilsonville, OR | ||||||||||||||||||||
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HyperLynx Signal Integrity Analysis
This course will help you understand basic signal integrity, crosstalk, EMI concepts and pre-and post layout stages of the design process. More upcoming dates (10 total)
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6/19/13 | Munich, DE |
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