Mentor Consulting Technical Publications

The OPC treatment of aerial mage ripples (local variations in aerial contour relative to constant target edges) is one of the growing issues with very low-k1 lithography employing hard off-axis illumination. The maxima and minima points in the aerial image, if not optimally treated within the existing model based OPC methodologies, could induce severe necking or bridging in the printed layout.

The current fragmentation schemes and the subsequent site simulations are rule-based, and hence not optimized according to the aerial image profile at key points. The authors are primarily exploring more automated software methods to detect the location of the ripple peaks as well as implementing a simplified implementation strategy that is less costly. We define this to be an adaptive site placement methodology based on aerial image ripples.

Recently, the phenomenon of aerial image ripples was considered within the analysis of the lithography process for cutting-edge technologies such as chromeless phase shifting masks and strong off-axis illumination approaches. Effort is spent during the process development of conventional model-based OPC with the mere goal of locating these troublesome points. This process leads to longer development cycles and so far only partial success was reported in suppressing them (the causality of ripple occurrence has not yet fully been explored). We present here our success in the implementation of a more flexible model-based OPC solution that will dynamically locate these ripples based on the local aerial image profile nearby the features edges. This model-based dynamic tracking of ripples will cut down some time in the OPC code development phase and avoid specifying some rule-based recipes.

Our implementation will include classification of the ripples bumps within one edge and the allocation of different weights in the OPC solution. This results in a new strategy of adapting site locations and OPC shifts of edge fragments to avoid any aggressive correction that may lead to increasing the ripples or propagating them to a new location. More advanced adaptation will be the ripples-aware fragmentation as a second control knob, beside the automated site placement.

In recent years, design for manufacturability (DfM) has become an
important focus item of the semiconductor industry and many new DfM
applications have arisen. Most of these applications rely heavily on the
ability to model process sensitivity and here we explore the role of
through-process modeling on DfM applications. Several different DfM
applications are examined and their lithography model requirements
analyzed. The complexities of creating through-process models are then
explored and methods to ensure their accuracy presented.

Device extraction and the quality of device extraction is becoming of increasing concern for integrated circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the design engineer faces the ever burgeoning demand of accurate device extraction. For technology nodes of 65nm and below approximation of extracting the device geometry drawn in the design layout polygons might not be sufficient to describe the actual electrical behavior for these devices, therefore contours from lithographic simulations need to be considered for more accurate results. Process window variations have a considerable effect on the shape of the device wafer contour, having an accurate method to extract device parameters from wafer contours would still need to know which lithographic condition to simulate. Many questions can be raised here like: Are contours that represent the best lithography conditions just enough? Is there a need to consider also process variations? How do we include them in the extraction algorithm? In this paper we first present the method of extracting the devices from layout coupled with lithographic simulations. Afterwards a complete flow for circuit time/power analysis using lithographic contours is described. Comparisons between timing results from the conventional LVS method and Litho aware method are done to show the importance of litho contours considerations.

This paper covers a project that is using advanced functional verification methods to verify a RTCA DO-254/EUROCAE ED80 Level A/B design. These methods include Constrained Random Simulation, Design Intent Specification (designer-added assertions), the Total Coverage Model (Unified Coverage Database), and Formal Verification (formal model checking). The project is a real design currently being developed at Rockwell Collins.

 Printed Circuit Board (PCB) electromagnetic compatibility (EMC) issues are becoming a bigger problem than ever before. Electronic products must now comply with more restrictive Federal Communications Commission (FCC) and European (CE) standards in order to be accepted into the marketplace. Technological advances have made complex electronics a major part of many product designs where they didn't previously exist. To make matters more difficult, very few engineering tools are available to prevent immunity issues and ensure that products meet EMC standards, and most of the methods used today are both time-consuming and costly. Due to the complexity of ensuring EMC compliance, many companies are turning to expert systems to solve their EMI issues. An expert system, such as the Mentor Graphics Quiet™ Expert tool, can gather PCB data and make value judgments based on EMC rules.

Intelligent allocation of systems and devices into the platform, and their subsequent interconnection via physical wiring, is a critical process that affects the quality and reliability of end products. In addition, design and manufacturing costs can be reduced by implementing processes and tools that facilitate the optimum design of the electrical system. The challenges associated with the deployment of systems and their electrical distributions are significant, and require a unique solution. The solution must automate device packaging in the car, and synthesize wiring within the available routing channels. This paper outlines an approach that results in the synthesis of an electrical interconnect system valid for all vehicle variants and options, available for simulation, high level analysis and downstream manufacturing operations.