White Papers

Advanced EDS Design Tools Pave the Way for a Transition to Electric Vehicles

Electric vehicle platforms bring with them a host of new challenges for designers. This white paper will explore how issues range from battery placement to electrical distribution to eliminating crosstalk... View White Paper

Wire Harness Manufacturing Process Management

Wire harnesses are vital components within modern transportation platforms such as aircraft and automobiles because they distribute power and signals between the various devices that deliver electrical... View White Paper

What Race Car Teams Can Learn from Passenger Car Designers

Racing design lags behind its peers in the commodity automobile industry in some key respects, particularly in the realm of electrical design. This paper explains how today’s automated ECAD tools,... View White Paper

Automotive Electrical Design with Manufacturing in Mind

The electrical distribution system design process for vehicles is basically a sequence of steps performed serially. Historically each step has been an “island” with its own design tools. This... View White Paper

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Why You Should Optimize Power at the ESL

The opportunities for optimizing a design for power are greatest at the architectural level of abstraction, where the design architecture is determined. The further a design moves downstream the less effective... View White Paper

Making the Case for HLS

Algorithms and architectures used in today’s new designs are so complex that traditional design practices are becoming inadequate. This paper gives an overview of the problems associated with the... View White Paper

Realizing ESL with Scalable Transaction Level Models

The OSCI TLM2 standard, scalable transaction-level models, and a methodology built around the Vista™ Model Builder technology overcome the three prevalent concerns about electronic system level design.... View White Paper

SystemC Modeling, Synthesis, and Verification in Catapult C

Catapult® C Synthesis added SystemC support for modeling, verification, and synthesis of complex ASICs at the system level. Both cycle-accurate and transaction-level (TLM) abstractions are supported,... View White Paper

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The Integrated IP Subsystem: A Converging SoC Solution

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude... View White Paper

The Evolution in Disk-Drive Storage: How Consumer Electronic Storage Devices will Drive Future Growth

The new CE-ATAinterface standard for handheld devices and consumer electronic portables is quickly emerging as the most promising storage interface standard today. Replacing SATA, CE-ATA addresses many... View White Paper

Ptolemy-Oriented Structural, Reconfigurable, and Heterogeneous Hardware Design, Verification and Synthesis

This paper investigates the suitability of Ptolemy II platform for current complex hardware systems design, modeling, simulation, verification, synthesis and implementation. Systems complexity, lower process... View White Paper

Analog IP Migration Using Design Knowledge Extraction 

Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. It relies on design knowledge extraction, which renders it very fast compared to full optimization... View White Paper

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Modern IC Packaging

Modern IC packaging technologies, such as 3D-IC, drive the need for IC, package and system co-design tools and methodologies. View White Paper

Ready for 3D-IC

This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon... View White Paper

3D-IC System Verification Methodology: Solutions and Challenges

Presents a verification methodology for 3D-ICs, including connectivity checking and parasitic extraction.  Discusses new challenges and EDA tools to responds to those challenges.  An example illustrates... View White Paper

Analyzing the Device Parasitics Sensitivity and Accuracy of Calibre xACT 3D Field Solver Extraction

As process technologies advance, a parasitic extraction tool requires more sophisticated extraction capability to obtain the effective sensitivity analysis users need, while still meeting schedules and... View White Paper

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Patterning Process Models Presentation

This presentation reviews the steady improvement in the predictive power and runtime performance of the patterning models used in full chip simulation tools down to 14 nm node, as well as the factors that... View White Paper

Challenges for Patterning Process Models Applied to Large Scale

Full-chip patterning simulation has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical... View White Paper

Improved Process Window Modeling Techniques

The continuous reduction of device dimensions and densities of integrated circuits increases the demand for accurate process window models used in optical proximity correction. Beam focus and dose are process... View White Paper

Contour-Based Self-Aligning Calibration of OPC Models

SEM contours are used to complement CD measurements in OPC model calibration. This is done to capture 2D information about printed features into the model while CD measurement data is kept to maintain accuracy... View White Paper

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Using Assertions to Satisfy Elemental Analysis

This paper discusses DO-254 and what it requires for verification (including advanced methods for DAL A/B designs), explains the original intent of Elemental Analysis, the way it is typically satisfied... View White Paper

Virtual Devices for Protocol-Specific Host and Peripheral Interfaces

This paper provides a brief genealogy of virtual devices, describes their characteristics and benefits, and presents two design applications that demonstrate its utility and effectiveness. View White Paper

Understanding electronic IP: common issues and how to find them

Using IP blocks in designs requiring DO-254 compliance is becoming more popular as a way to reduce costs and schedules. However, the use of IP comes with its own problems and pitfalls. A good methodology... View White Paper

Using Formal Verification to Check SoC Connectivity Correctness

Formal verification offers a solution that is quick, exhaustive and allows for efficient debug. It’s true that traditionally, chip-level formal verification is impractical. The approach usually targets... View White Paper

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Cross Design Team Interconnect Planning

John Park, Business Development Manager and Methodology Architect for Mentor’s System Design Division, discusses the growing interactions among IC, packaging and PCB design flows. View White Paper

Need to Save PCB Design Time? Winning in Electronics by Managing Printed Circuit Board Data

While all industries struggle with time-to-market pressures, this pressure is even more intense in the electronics industry. The speed at which technologies evolve and competitors either introduce new products... View White Paper

Designing Modern 3D Packages with Mixed Technology Content

We are faced with designing extremely high performing packages with mixed technology content such as high speed digital, analog, and RF. At the same time, the density requirements are forcing us to use... View White Paper

Cross Design Team Interconnect Planning

Interconnect and I/O planning between the design teams for IC layout, Package substrate design, and printed circuit board (PCB) layout is critical to driving down costs for the package and the PCB. Companies... View White Paper

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Using Assertions to Satisfy Elemental Analysis

This paper discusses DO-254 and what it requires for verification (including advanced methods for DAL A/B designs), explains the original intent of Elemental Analysis, the way it is typically satisfied... View White Paper

Using FPGA Synthesis to Protect Against Radiation Effects and Soft Errors

Mentor Graphics Precision® Hi-Rel automatically incorporates advanced mitigation circuitry during device-neutral RTL synthesis, thereby providing additional protection through the implementation flow... View White Paper

Understanding electronic IP: common issues and how to find them

Using IP blocks in designs requiring DO-254 compliance is becoming more popular as a way to reduce costs and schedules. However, the use of IP comes with its own problems and pitfalls. A good methodology... View White Paper

Best practice development processes for medical device FPGAs

For FPGA developers working on designs for medical devices, one approach to dealing with regulatory uncertainty is to borrow heavily from design assurance processes in other safety-critical industries,... View White Paper

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Ready for 3D-IC

This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon... View White Paper

Low Power Test

Today’s advanced integrated circuit (IC) designs are increasing in complexity, with their seemingly endless progression to smaller geometries, ever increasing integration between analog and digital... View White Paper

User Defined Fault Models

This white paper describes the functionality of user defined fault models (UDFM), including gate exhaustive UDFM and cell-aware UDFM, and the effectiveness of lowering DPM in devices. View White Paper

High Quality Test of ARM® Cortex™-A15 Processor Using Tessent® TestKompress®

This white paper provides a high level overview of the Mentor reference flow for ARM architecture. View White Paper

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A Requirements-Driven System Design Process (with a Preview of ARP 4754A)

This presentation, which was delivered at IESF Mil-Aero in Long beach, CA, on Sept 13, 2011, discusses the importance of a requirements-driven systems development process. It also introduces the new regulatory... View White Paper

Concept to X

This paper describes ten steps to applying Model Driven Development (MDD) to your design process and shows that the process is neither alien to current thinking, nor impossibly expensive to implement. View White Paper

Robust Analysis for Switch-Mode Power Supply Designs

This paper illustrates the use of several robust analysis options available with the SystemVision simulation tool. Both parametric and statistical analyses are presented using a buck-boost converter as... View White Paper

Understanding DO-254 and Solutions to Facilitate Compliance

RTCA/DO-254 (also known as DO-254 in the US or ED-80 in Europe) provides guidelines to facilitate requirements-based design of airborne electronic hardware. Now mandated by the US Federal Aviation Association... View White Paper

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Step by Step...Confidently: Through the AUTOSAR Round Trip

This paper demonstrates the interaction and the interoperability of architecture and model-based design environments in five steps using the examples of MATLAB, Simulink, and Embedded Coder by MathWorks,... View White Paper

Round-Trip Engineering Key to AUTOSAR-based Development

This paper discusses how round-trip engineering can be used as an iterative development process and describes interoperability between tools from Mentor and MathWorks. View White Paper

The Electrifying Side of AUTOSAR: The Case for Using the ECU Resource Template

This paper describes a meta-model that covers specific portions of software-oriented AUTOSAR development methodology using the ECU Resource Template. View White Paper

Top-down Design of Distributed Embedded Systems in Light of Timing Considerations

Proper safeguarding of safety-critical systems in an automotive environment cannot be ensured sufficiently without taking timing into consideration. The failure to observe timing constraints can lead to... View White Paper

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