Technical Publications
Design Area:Electrical & Wire Harness Design
New Tools Answer Old Issues in Wiring Harness Design
Building automotive wiring harnesses is a tough business; one in which only the strong survive. Harness makers must deliver products that are ever more complex. They also must offer steadily improving quality.... View Techpub
The Aerospace Industry Takes a Fresh Look at Its Wire Harness Design Approach
The aerospace industry has long been perceived as slow to adapt to new wire harness engineering technologies and processes. Many enterprises rely on systems created in-house, with each tool being structured... View Techpub
Taking Wiring Design to the Next Level
In this paper, the problem of wiring complexity that confronts electronic and electrical (EE) design engineers in the automotive, trucks and off-road industries will be discussed. The forces driving growing... View Techpub
Making the Most of Electrical Simulation in the MCAD/PLM World
Modern equipment such as automobiles, aircraft or robots can be thought of as complex electromechanical assemblies. Commercial imperatives of reduced time to market, improved quality and minimized total... View Techpub
Design Area:Electronic System Level Design
Realizing ESL with Scalable Transaction Level Models
The OSCI TLM2 standard, scalable transaction-level models, and a methodology built around the Vista™ Model Builder technology overcome the three prevalent concerns about electronic system level design.... View Techpub
SystemC Modeling, Synthesis, and Verification in Catapult C
Catapult® C Synthesis added SystemC support for modeling, verification, and synthesis of complex ASICs at the system level. Both cycle-accurate and transaction-level (TLM) abstractions are supported,... View Techpub
Boosting RTL Verification with High-Level Synthesis
Instead of prolonging the painful process of finding bugs in RTL code, the design flow needs to be geared toward creating bug-free RTL designs. This can be realized today by automating the generation of... View Techpub
Advanced Clock Gating Techniques in Catapult C Synthesis
This whitepaper discusses one of the most important power optimization techniques used in Catapult C Synthesis – advanced clock gating optimization and analysis. Electronic System Level (ESL) design... View Techpub
Design Area:Embedded Systems
How to Rapidly Create and Customize Compelling GUIs for Android-Based Devices
This paper takes a closer look at one available GUI technology that allows for the rapid creation and radical customization of a GUI in any Android-based device. View Techpub
How Multicore Enables the Fast and Efficient Deployment of Multi-OS Systems
This paper discusses how multicore designs are creating the need for a true multi-OS system. Within this discussion Symmetric Multi-Processing (SMP), Asymmetric Multi-Processing (AMP), multicore hardware... View Techpub
Getting Started With Android Development for Embedded Systems
This paper takes a look at the design of Android, how it works, and how it may be deployed to accelerate the development of a connected device. Along with basic guidelines to getting started with Android,... View Techpub
Effective Embedded Differentiation with Graphical User Interfaces
In today’s competitive embedded markets, manufacturers need to find ways to differentiate without adversely impacting development time and cost. This is particularly true in relation to embedded devices... View Techpub
Design Area:Intellectual Property
PCIe - Sizing Replay Buffer Appropriately and Achieving High Throughput in the Process
PCI Express is the latest generation I/O technology for high performance chip-to-chip interconnect applications. The overall performance of the PCI Express system depends on how quickly the data flows... View Techpub
PCIe - A Technology-Laden Communications Interface for the Future
The increasing I/O bandwidth requirement and decreasing real-estate requirements of the end product necessitate the adoption of faster I/O interconnect technology. The latest PCI Express technology is the... View Techpub
The Integrated IP Subsystem: A Converging SoC Solution
The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude... View Techpub
The Evolution in Disk-Drive Storage: How Consumer Electronic Storage Devices will Drive Future Growth
The new CE-ATAinterface standard for handheld devices and consumer electronic portables is quickly emerging as the most promising storage interface standard today. Replacing SATA, CE-ATA addresses many... View Techpub
Design Area:IC Design
Multi-Voltage Design Flow with Olympus-SoC
In this paper, we will explore the multi-voltage design flow that is currently used in low power IC design, describe the primary challenges of the multi-voltage flow, and discuss the completely automated... View Techpub
Combining Low Pin Count Test with Scan Compression Dramatically Reduces Test Interface and Cost
The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand... View Techpub
Advanced Floorplanning with Olympus-SoC
As the first step in a netlist-to-GDSII design flow, floorplanning presents the SoC designer with challenges and opportunities that affect the rest of the design flow, from block implementation, to chip... View Techpub
Automated DRC Waiver Management (or, How I Learned to Stop Worrying About IP Waivers and Love Calibre Auto-Waiver)
This paper explains the Calibre Auto-Waiver product, and discusses how the auto-waiver process significantly reduces the time and risks associated with implementing third-party IP. View Techpub
Design Area:IC Manufacturing
Hierarchical DPT Mask Planning For Contact Layer
This paper investigates contact layer mask planning for DPT, and presents results on two new problems due to hierarchical processing. View Techpub
Effect of SRAF Placement on Process Window for Technology Nodes that Uses Variable Etch Bias
As technology advances to 45 nm node and below, the induced effects of etch process have an increasing contribution to the device critical dimension error budget. Traditionally, original design target shapes... View Techpub
pRSM: Models for Model-Based Litho-Hotspot Repairs
Computing repair hints for litho hotspots is made more effective with a model of how Process Window contour bands changes as a function of design layout changes. We have developed a modeling methodology... View Techpub
A User-programmable Link between Data Preparation and Mask Manufacturing Equipment
In order to fully exploit the design knowledge during the operation of mask manufacturing equipment, as well as to enable the efficient feedback of manufacturing information upstream into the design chain,... View Techpub
Design Area:Functional Verification
Using inFact with OVM Sequences
Most OVM users understand how OVM sequences can be used for stimulus generation, implemented as either a directed or constrained random test. However, they may not be aware that this same OVM sequence construct... View Techpub
Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools
DO-254 compliance is becoming increasingly common on commercial and military aviation projects. Companies often struggle with the requirements and costs of DO-254 compliance. Engineers can use Model-Based... View Techpub
Improving PCI-E DUT Verification
PCI Express (PCIe) is a complex protocol, which invariably leads to a staggering number of possible scenarios and corner cases during verification of any PCIe design under test (DUT). All PCI express RTL... View Techpub
With a Boost from OVM, SuperSpeed USB3.0 MVC BFM Accelerates Verification
The need to deal with verification is spurring a wave of technological experimentation across EDA. Though at best most such experiments result in incremental improvement, collectively the work adds up to... View Techpub
Design Area:PCB Systems
Power Integrity in Systems Design: Part 1
This paper discusses the fundamental requirements of power integrity (PI), and the most important concept used in PI, the network impedance. It answers the questions commonly asked by digital designers... View Techpub
BGA Breakouts and Routing
This book presents a number of studies and solutions for addressing these challenges. View Techpub
Fast, Robust S-parameter Modeling in HyperLynx GHz
The HyperLynx product suite from Mentor Graphics leads the market in mainstream signal integrity tools because of its intuitive and easy to use interface combined with its accurate and robust simulation... View Techpub
Accurate, Multi-GBPS Serial Channel Design Solutions for the Entire Design Team
This document describes of the advantages of deploying HyperLynx to meet the increasingly complex challenges of high speed channel design. An overview is provided of the advanced analysis technology. Finally... View Techpub
Design Area:FPGA
Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools
DO-254 compliance is becoming increasingly common on commercial and military aviation projects. Companies often struggle with the requirements and costs of DO-254 compliance. Engineers can use Model-Based... View Techpub
Using HDL Designer to Facilitate DO-254 Compliant and Safety-Critical Design Processes
DO-254 is a recent challenge facing aerospace companies, and in some cases, companies serving other safety- and mission-critical markets. HDL design falls under the DO-254 lifecycle category “Detailed... View Techpub
The Pivot Point for Design Flow Improvements
Due to its placement at the junction between design creation and physical implementation, FPGA synthesis can provide significant leverage in meeting quality goals and reducing project cost and time. For... View Techpub
Keep Your FPGA Options Open With Vendor-Independent IP
This white paper introduces and advocates tools that allow designers to create vendor-independent FPGA configurations that can change as new technologies and customer demands emerge. Third-party IP... View Techpub
Design Area:Silicon Test and Yield Analysis
Combining Low Pin Count Test with Scan Compression Dramatically Reduces Test Interface and Cost
The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand... View Techpub
Running Scan Test On Three Pins: Yes We Can!
Imagers are pretty little objects nowadays, their size is always shrinking and having only three standard digital pins available on their package is a most common thing. Looking back in 2006, only three... View Techpub
Comprehensive Hierarchical DFT for System-On-chip Devices, Tessent SoCScan Technology Backgrounder
Designers of large System-On-Chip (SOC) chips have increasingly adopted hierarchical design practices in order to more efficiently complete work at the core level and simplify integration at the SOC level.... View Techpub
Faster Time to Root Cause with Diagnosis-Driven Yield Analysis
This whitepaper describes the benefits of implementing a diagnosis-driven yield analysis flow using the Tessent™ Diagnosis and Tessent YieldInsight™ software products. View Techpub
Design Area:System Modeling
Simulating Vector Controlled Induction Motors Using Space Vector Modulation
This paper illustrates the development of a comprehensive vector-controlled induction motor drive system. Power delivery schemes will also be implemented and analyzed, including current-regulated pulsewidth... View Techpub
AUTOSAR and FlexRay: A Tale of Two Standards
The emerging automotive design software standard known as AUTOSAR (Automotive Open System Architecture) began as the product of an industry-wide effort among European auto makers and their suppliers. Its... View Techpub
Mechatronic System Integration and Design
While today’s multi-discipline mechatronic systems significantly outperform legacy systems, they are also much more complex by nature—requiring close cooperation between multiple design disciplines... View Techpub
Simulation Provides Key to Explosive Automotive Design Challenges
Not only has the typical system design grown in overall size to accommodate ever-increasing demands for functionality and performance, but these designs must fluently integrate analog and digital hardware,... View Techpub
Design Area:Vehicle Network Design
AUTOSAR and FlexRay: A Tale of Two Standards
The emerging automotive design software standard known as AUTOSAR (Automotive Open System Architecture) began as the product of an industry-wide effort among European auto makers and their suppliers. Its... View Techpub
Developing Automotive Products Using the EAST-ADL2, an AUTOSAR Compliant Architecture Description Language
Current development trends in automotive software feature increasing standardization of the embedded software structure. But, it still remains the critical issue of the overall engineering information management... View Techpub
Designing and Implementing Architectures for Distributed Automotive E/E Systems
The complexity of electrical and electronic systems in cars has grown drastically during the past decade. Model-based function design and simulation are widely used by the Automotive E/E community today... View Techpub
Experimental Jitter Analysis in a FlexCAN-based Drive-by-Wire Automotive Application
This paper describes several experiments designed to characterize jitter in an actual automotive application designed using FlexCAN, a CAN-based communication architecture. Large and variable jitter has... View Techpub