Technical Publications
Design Area:Electronic System Level Design
Advanced Clock Gating Techniques in Catapult C Synthesis
This whitepaper discusses one of the most important power optimization techniques used in Catapult C Synthesis – advanced clock gating optimization and analysis. Electronic System Level (ESL) design... View Techpub
A Scalable Approach for TLM Across SystemC and SystemVerilog
There are a number of compelling reasons that SystemC and SystemVerilog should co-exist in advanced verification environments. Hence, many attempts have been made to mix the two languages. The paper addresses... View Techpub
Hardware/Software Validation with a TLM Virtual System Prototype
With all the complexity associated with the hardware, the software is also crucial to the competitive success of these products. The application software often is the key differentiator for these consumer... View Techpub
Using High-Level Synthesis for FPGA Development
Next generation communication systems (Super 3G, WiMAX, etc.) will enable telecommunications carriers to deliver enhanced multimedia services at super-high-speeds. However, designing the hardware to support... View Techpub
Design Area:Embedded Systems
Microtec C/C++ Compiler Toolkit for PowerPC
Embedded developers need a set of compiler tools that can take high-level languages such as C, C++, or assembly language, and produce reliable code for their embedded target. These development tools should... View Techpub
Simtest Simulation: A Powerful Tool for Embedded Software Development
Embedded software is no longer written in assembly language macros. In fact, the same high-level languages and tools used for writing embedded software are the same tools used for designing application... View Techpub
Prevention is Better Than the Cure: Compiler Run-Time Error Checking
Compilers are generally thought of as being tools that convert a high level language, like C or C++, into assembler or machine code. Of course, they do perform this function, but have the potential to do... View Techpub
Advantages of Host Simulation Over Other Types of Embedded Software Simulators
During the last decade, embedded software’s nature in devices has changed radically. As devices have taken on increasingly more functionality, the complexity of higher level software has grown accordingly.... View Techpub
Design Area:Intellectual Property
PCIe - Sizing Replay Buffer Appropriately and Achieving High Throughput in the Process
PCI Express is the latest generation I/O technology for high performance chip-to-chip interconnect applications. The overall performance of the PCI Express system depends on how quickly the data flows... View Techpub
PCIe - A Technology-Laden Communications Interface for the Future
The increasing I/O bandwidth requirement and decreasing real-estate requirements of the end product necessitate the adoption of faster I/O interconnect technology. The latest PCI Express technology is the... View Techpub
The Integrated IP Subsystem: A Converging SoC Solution
The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude... View Techpub
The Evolution in Disk-Drive Storage: How Consumer Electronic Storage Devices will Drive Future Growth
The new CE-ATAinterface standard for handheld devices and consumer electronic portables is quickly emerging as the most promising storage interface standard today. Replacing SATA, CE-ATA addresses many... View Techpub
Design Area:IC Design
Layout Pattern Dependence-Aware Highly Accurate Simulation Flow with Calibre nmLVS
In today’s nanometer processes, the “layout pattern dependence” that causes variations in the electrical characteristics due to the shape around MOSFETs is becoming more significant. In response to this,... View Techpub
Chip-Scale Copper Electroplating and CMP Simulator
Mentor Graphics has developed a chip-scale copper electroplating and chemical-mechanical polishing simulator called CMP Optimize. CMP Optimize is part of the Calibre® WORKBench™ platform, and... View Techpub
Signal Integrity Optimization with Olympus-SoC
This paper explores the techniques for signal integrity prevention and repair in the Olympus-SoC place and route system. Signal integrity (SI) is a growing problem as higher interconnect density, increasing... View Techpub
A Case Study: Critical Area and Critical Feature Analysis of Production 90nm Designs at LSI Corporation
This paper documents the results of a critical area and critical feature analysis study of four LSI production 90 nm designs. The recommended rule adherence and statistical sensitivity to random particle... View Techpub
Design Area:IC Manufacturing
Chip-Scale Copper Electroplating and CMP Simulator
Mentor Graphics has developed a chip-scale copper electroplating and chemical-mechanical polishing simulator called CMP Optimize. CMP Optimize is part of the Calibre® WORKBench™ platform, and... View Techpub
Design Driven Test Patterns for OPC Models Calibration
In the modern photolithography process for manufacturing integrated circuits, geometry dimensions need to be realized on silicon which are much smaller than the exposure wavelength. Thus Resolution Enhancement... View Techpub
Model-Based Retarget for 45nm Node and Beyond
To overcome the limitation of table-driven retargeting, we developed model-based retarget. If we set the criteria of process window, OPC tool resizes the layout dimension automatically. OPC tool will do... View Techpub
OPC for Reduced Process Sensitivity in the Double Patterning Flow
The pitch-splitting of patterns using the litho-etch-litho-etch double patterning technique (DPT) may be required at both 32nm and 22nm nodes. By splitting the layout into two masks, DPT introduces some... View Techpub
Design Area:Functional Verification
A Closer Look at Veloce Technology: Taking Hardware-assisted Verification to the Next Level
Chip and verification complexities continue to grow. Despite these growing complexities, time-to-market pressures require that chip verification be completed on schedule. Hardware-assisted verification... View Techpub
Using Parameterized Classes and Factories: The Yin and Yang of Object-Oriented Verification
This paper will introduce the factory pattern, which has been used with parameterized classes as a proven technique for writing reusable verification class components, and it will provide examples along... View Techpub
Improving Efficiency, Productivity, and Coverage Using SystemVerilog OVM Registers
A subset of the currently used solutions will be described in this paper, followed by a list of register verification requirements, a description of some register testing styles and modes, along with a... View Techpub
Is There a Future for SystemVerilog Interfaces?
The SystemVerilog interface is intended to be a powerful modeling construct for describing hardware interconnect in a very general manner that is applicable to both testbench and synthesizable RTL design... View Techpub
Design Area:PCB Systems
Opening Eyes on Fiber Weave and CAF
The signal channels that link high speed processors to memory and various other peripherals, are limited by the inherent characteristics of the printed circuit board. These are what ultimately connect information... View Techpub
The Developing Technologies of Integrated Optical Waveguides in Printed Circuits
High Density Interconnect (HDI) printed circuits are now being designed in ever-increasing quantities for very high speed applications. The challenge of opto-electronics and integration of photonics into... View Techpub
Establishing Confidence in PDN Simulation
A powerful signal integrity analysis tool must be flexible, easy to use and integrated into an existing EDA framework and design flow. In addition, it is important for the tool to be accurate enough. This... View Techpub
Measuring the Performance of Equalized Serial Data Links Across the Design Flow
For advanced signaling over high-loss channels, designs today are using equalization and several new measurement methods to evaluate the performance of the link. Both simulation and measurement tools support... View Techpub
Design Area:FPGA
Making the Case For an Integrated FPGA Design Flow
With the rate of ASIC-to-FPGA conversions continuing to escalate, choosing the right FPGA design tools can determine the course and competitiveness of a system house’s entire business. Design teams... View Techpub
Designing Multi-FPGA Prototypes That Act Like ASICs
FPGA prototyping has become indispensable for functional verification and early software integration of prospective ASIC designs. If the ASIC in question is large, it is often necessary to spread the functionality... View Techpub
Block-Based FPGA Design Flows Support Team Design and IP Re-use
Block-based design—a method of partitioning a complex FPGA design into natural sub-blocks—has become a necessity for many project teams. It not only streamlines the design and integration process... View Techpub
Code Coverage Explained: For DO-254 Projects
Level A/B designs governed by RTCA/DO-254 must have additional verification for added design assurance. DO-254 Appendix B specifies several methods by which this can be accomplished. Today, the most common... View Techpub
Design Area:Silicon Test and Yield Analysis
Combining Compression with Fewer Pins Dramatically Saves I/O during Multi-Site Test
The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand... View Techpub
Layout-Aware Diagnosis
Scan logic diagnosis is a powerful tool to help failure analysis engineers determine the root cause of a failing die. Yield engineers, on the other hand, are interested in statistical analysis of volumes... View Techpub
Beyond Pass/Fail Testing: Using Failure Data from Manufacturing Test for Yield
As feature sizes shrink, the number of non-visual defects increases. At the same time, traditional methods for defect identification and yield learning are becoming less effective. Scan design has been... View Techpub
Achieving High-Quality Test for ARM Artisan Memories
High quality testing of today's nanometer designs is increasingly more essential - and more complicated. One aspect of this, memory testing, is becoming more of a concern as well. Not only is the amount... View Techpub
Design Area:System Modeling
Reducing Development Program Risk
This paper describes how incorporating a model-driven development process into the development life cycle lays the groundwork for an integrated design flow. This process helps address systems integration... View Techpub
Modeling a Digitally Controlled Power Supply
Power supply designs are going digital. It is now common to see what would have once been a completely analog design incorporate some combination of Digital Signal Processing (DSP), microcontroller (uC),... View Techpub
How to Model Power Systems Using SystemVision
This booklet introduces practical guidelines and specific techniques for developing and analyzing complex power systems with the aid of computer simulation. The general concept of computer simulation... View Techpub
CAN Bus Signal Integrity Design
VHDL-AMS (IEEE Standard 1076.1) provides hardware modeling capabilities that are well suited for CAN signal integrity analysis. This includes modeling the analog, digital and mixed-signal aspects of the... View Techpub
Design Area:Electrical Systems and Harness
Accelerating Wire Harness Development for Off-Highway Vehicles
Manufacturers of off-highway vehicles are faced with the same challenges as companies in other sectors reducing design and manufacturing costs, reducing lead times, and improving product quality. Today,... View Techpub
Electrical and Mechanical Integration in Automotive and Aerospace Design
This paper addresses the issue of increasing complexity of today's automotive and aerospace electrical systems. Manufacturers now seek a high degree of integration between their business and design tools. ... View Techpub
Automating Systems Integration and Electrical Distribution in Modern Car Platforms
Intelligent allocation of systems and devices into the platform, and their subsequent interconnection via physical wiring, is a critical process that affects the quality and reliability of end products.... View Techpub
Using Standards to Build a Stable Framework for Product and Market Development
This paper discusses the role of data exchange Standards in building a framework for the seamless flow of data between suppliers and manufacturers with particular reference to the use of AP212 and KBL in... View Techpub
Design Area:Vehicle Network Design
Developing Automotive Products Using the EAST-ADL2, an AUTOSAR Compliant Architecture Description Language
Current development trends in automotive software feature increasing standardization of the embedded software structure. But, it still remains the critical issue of the overall engineering information management... View Techpub
Designing and Implementing Architectures for Distributed Automotive E/E Systems
The complexity of electrical and electronic systems in cars has grown drastically during the past decade. Model-based function design and simulation are widely used by the Automotive E/E community today... View Techpub
Experimental Jitter Analysis in a FlexCAN-based Drive-by-Wire Automotive Application
This paper describes several experiments designed to characterize jitter in an actual automotive application designed using FlexCAN, a CAN-based communication architecture. Large and variable jitter has... View Techpub
In-Vehicle Network Design Methodology
The complexity of in-vehicle networks puts the traditional design processes to a test. Last minute changes, difficult verification, testing, and similar issues add to the challenges. However, changing the... View Techpub