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The number one reason for the use of SystemC is the significantly increased simulation performance at the TLM level over executable platforms modeled at the RT level using Verilog or VHDL. SystemC TL models are fast enough to serve as a software development platform allowing for early software development and for co-simulation of hardware and software. Both TL and functional models are fast enough for system level architectural modeling and analysis.

The second reason for SystemC use is functional verification. The same executable platform that is used to develop the software is often used for verification of the entire system. This verification occurs early on in a project and the TLM becomes a golden reference for the entire system. Because SystemC is C++, it has a number of inherent properties, such as classes, templates and inheritance, that lend themselves to verification. These capabilities are extended with the SystemC Verification Library (discussed later) making SystemC a powerful verification language as well as modeling language.

This exhaustive examination includes dozens of graphics, a glossary and code appendix.

With all the complexity associated with the hardware, the software is also crucial to the competitive success of these products. The application software often is the key differentiator for these consumer products, allowing the system company to reap substantial profit margins. Software is also key in the power and performance behavior of the hardware platform.

The number one reason for the use of SystemC is the significantly increased simulation performance at the TLM level over executable platforms modeled at the RT level using Verilog or VHDL. SystemC TL models are fast enough to serve as a software development platform allowing for early software development and for co-simulation of hardware and software. Both TL and functional models are fast enough for system level architectural modeling and analysis.

The second reason for SystemC use is functional verification. The same executable platform that is used to develop the software is often used for verification of the entire system. This verification occurs early on in a project and the TLM becomes a golden reference for the entire system. Because SystemC is C++, it has a number of inherent properties, such as classes, templates and inheritance, that lend themselves to verification. These capabilities are extended with the SystemC Verification Library (discussed later) making SystemC a powerful verification language as well as modeling language.

This exhaustive examination includes dozens of graphics, a glossary and code appendix.

The number one reason for the use of SystemC is the significantly increased simulation performance at the TLM level over executable platforms modeled at the RT level using Verilog or VHDL. SystemC TL models are fast enough to serve as a software development platform allowing for early software development and for co-simulation of hardware and software. Both TL and functional models are fast enough for system level architectural modeling and analysis.

The second reason for SystemC use is functional verification. The same executable platform that is used to develop the software is often used for verification of the entire system. This verification occurs early on in a project and the TLM becomes a golden reference for the entire system. Because SystemC is C++, it has a number of inherent properties, such as classes, templates and inheritance, that lend themselves to verification. These capabilities are extended with the SystemC Verification Library (discussed later) making SystemC a powerful verification language as well as modeling language.

This exhaustive examination includes dozens of graphics, a glossary and code appendix.

Louis Baguena, ASIC/FPGA Design Manager at Alcatel Space states, "Using our traditional RTL flow, three blocks took approximately nine weeks to design. Once we were up to speed on Catapult C Synthesis, all three blocks were done in three weeks starting from the original untimed C++ source, representing an impressive 3X improvement".

This comprehensive case study shows how Alcatel addressed their satellite hardware design needs. Learn how Alcatel was able to leverage the same pure, untimed C++ already written by the system designer to create hardware using the Catapult C Synthesis tool. The Alcatel case study compares the traditional manual RTL flow with the new C based design flow using Catapult C Synthesis.

This report discusses the hardware implementation of “eigenvalue decomposition”. Eigenvalue decomposition is used in a wide range of applications for imaging, communication and audio such as image recognition using KL conversion, high-speed communication using MIMO antenna, and electric/sound wave arrival direction estimation using MUSIC method. It is expected that more than four antennas will be required in many cases for future MIMO communications and electric wave arrival direction estimation with MUSIC method applications. Here we were interested in verifying whether the method to obtain eigenvalues directly from the eigenvalue equation was reasonable or not. Therefore, we developed two effective algorithms in ANSI C++ to obtain eigenvalues and synthesized them with Catapult C Synthesis to compare the area versus the number of cycles at the algorithm level, respectively.

Dennis McCain, Research Manager at Nokia Research Center states, "When we started evaluating Catapult C, we quickly realized that we had found a winning solution. However, we had no conception that we?d move from using this tool in a beta site evaluation role to using it for mission-critical portions of our design so quickly."

This case study explains why Nokia's evaluations were so successful that Catapult^TM C Synthesis ended up being used for the mission-critical portions of the design.

This white paper first introduces conventional design flows and examines the associated problems that system architects and hardware designers face today. The paper next considers alternative approaches to hardware design based on the use of C and C++, including SystemC, Handel-C, and the synthesizable subset of pure untimed C++ used by Mentor's new Catapult? C Synthesis tool. The final sections in this white paper presents real world results outlining the increased productivity and implementation flexibility experienced by an R&D team using a Catapult C-based flow at the Nokia Research Center.

Next generation communication systems (Super 3G, WiMAX, etc.) will enable telecommunications carriers to deliver enhanced multimedia services at super-high-speeds. However, designing the hardware to support these systems has become more and more complicated. To implement these demands into an ASIC or FPGA, one must consider tradeoffs between design time, the size of the silicon implementation, and performance of the final system. Even more challenging, one must complete these larger, more complex designs faster to meet their tight time-tomarket windows. Thus, we have to introduce a new design methodology such as C-Based design.

Today's class of high-performance FPGAs such as the Altera Stratix III provide design engineers with a hardware platform that is capable of addressing the computational requirements needed to implement many of the next-generation wireless and video algorithms. Although these devices provide dedicated hardware to implement the basic building blocks of digital signal processing (DSP) algorithms such as multiply-accumulate (MAC), designers still must meet the challenges of rapidly taking an algorithm from concept to implementation in RTL.

Historically, the design flow consisted of modeling the algorithm functionality in a high-level language such as C++ and then hand-coding it in RTL. This manual method of RTL creation is not only time consuming and error prone, but often is highly sensitive to back-end routing delay problems. Catapult High-level C++ synthesis has historically been used to build ASIC hardware sub-systems found in extremely complex and compute intensive applications found in wireless, video and image processing. Combining Catapult's ASIC capabilities with Altera Accelerated Libraries provides designers with a rapid path from algorithms modeled in ANSI C++ to optimized RTL running in FPGA hardware. Furthermore, this design flow allows designers to directly target the FPGA DSP blocks from C++, easily solving back-end timing problems using high-level synthesis constraints.

Peter Nord, EDA and Methodology Coordination, Ericsson Mobile Platforms states, "Being able to achieve a 31 percent reduction in gate count, which correlates closely to silicon real estate and power consumption, speaks for itself. The cooperation between Mentor Graphics and Ericsson to develop a C-based tool that meets our requirements has been fantastic."

In this extensive case study you will see how Catapult C Synthesis addresses the classic RTL bottleneck faced by Ericsson's ASIC design teams. Ericsson discusses existing design challenges using traditional RTL design flows and barriers they face. The case study discusses how Ericsson was able to perform frequency exploration on a wider micro-architecture design space. Ericsson discusses how this new approach yielded designs which were 20-30% smaller than hand coded methods when running at the same design latency.

Many RTL designs are developed from C++ algorithms that have been extensively tested using a C++ testbench. The C++ testbench often represents a huge engineering effort to provide as much coverage of the algorithm as possible. Once the algorithm has been synthesized to RTL, however, a new testbench is typically written instead of using the original C++ testbench. This creates a discontinuity between the verification performed on the sequential untimed C++ algorithm and the resulting RTL. This paper describes a methodology for performing Functional Verification between the original C++ and the RTL using a C++ testbench in a SystemC framework. Such a framework enables detecting errors in the RTL due to assumptions made during the synthesis of the C++ and avoids errors introduced in re-writing the testbench at the RTL level. Topics such as datatype conversion and transaction synchronization will be covered.

Hardware implementations of DSP designs typically start out as algorithms modeled in tools like Matlab(tm). Such tools provide a natural representation of the algorithm and an extensive collection of building blocks used to analyze algorithm performance, both quantitatively (S/N, BER, quantization errors, etc) and qualitatively (spectrum displays, processed image viewing, etc). They can also provide a quantitative analysis of possible fixed point implementations (rounding and saturation errors). However, as the design then moves to implementation in FPGA or ASIC hardware, the design must be recoded in a hardware description language (HDL) for synthesis. Verification of the recoded design using the original modeling tool becomes awkward and subject to human error as data files of input stimuli and responses are passed to and from the analysis tool. This paper outlines an alternate approach that uses C++ to code the initial algorithm, C++ software libraries of analysis functions for performance testing, an ESL synthesis tool to synthesize the C++ to HDL and a SystemC framework to verify the correct behavior of each synthesis transformation of the algorithm against the original C++. The result is a comprehensive DSP development environment with analysis and verification at any point from algorithm to FPGA/ASIC gate-level simulation.

Block-based design, where prefabricated IP is configured and integrated into designs, will become the key productivity driver for designers in the next decade.  A large proportion of new designs will be based on currently existing design subsystems configured in new and interesting ways.  Embracing the new technologies and understanding of IP--and understanding how IP will be used by designers who are under severe pressure to create working designs in the shortest possible time--will be the key to creating an environment where prefabricated IP underpins the majority of new designs.

As the complexity of SoC devices rises to include scores of distinct blocks, system validation becomes a critical concern. A variety of techniques have emerged to help designers verify that individual blocks of a device meet performance specifications but validating functional intent in a system context is a relatively new challenge for hardware designers. This article outlines an approach for high-level system validation before RTL implementation and presenta a flow to achieve this increasingly essential task.

Today's incredibly large and complex digital ICs (ASICs, ASSPs, and SoCs) can easily contain tens of millions of logic gates. The only realistic way to create and verify designs of this size and complexity is to use a mixture of pre-defined intellectual property (IP) blocks and application-specific logic.

In this case, the pre-defined IP blocks - which may be internally developed, but which are often acquired from third-party vendors - are used to implement well-known functions such as general-purpose microprocessor cores, special-purpose digital signal processor cores, peripheral functions, memory interfaces, and high-speed data interfaces. This leaves the designers free to focus their time and resources on the application-specific ("secret sauce") logic that will differentiate this product from any competitor offerings.

Winter Quarter Newsletter
This issue includes articles on micro-ITRON, Debugging Techniques with an RTOS, Radio Astronomy and Technical Support.

Embedded devices have become an ever present part of our everyday lives. As the significance of the software part of embedded devices continues to steadily grow, its size and complexity keeps increasing. This trend, along with the fact that applications are becoming more and more connected via various protocols, dramatically increases the complexity of the whole system.

In this context, traditional system integration and testing methods based on hardware prototypes are becoming inadequate. It has been estimated that for distributed systems having soft real-time requirements, 50% of the software development time was spent on verifying the functionality. For systems having hard real-time requirements, testing and verification tasks could take up to 70% of the development time. The traditional development cycle, where module testing is based on Instruction Set Simulators (ISS) and integration testing is performed with hardware prototypes, has several drawbacks. Such an environment is inflexible and hard to deploy across an organization. Moreover, it usually requires hardware updates and reconfiguration from one project to another, which reduces cost effectiveness of the approach. But the main drawback lies in the process itself, where code is developed in the workstation environment and later tested and integrated in the target environment. The first time application is tested in full system context where it can interact with the peer devices and humans occur very late in the project. This contradiction is the source of all the major bottlenecks and sets a clear need for new development and verification methods. In this paper, we describe the EDGE SimTest prototyping environment that addresses these development problems.

Answering the unique needs of embedded developers, Accelerated Technology has developed Nucleus Embedded Developers Graphical Environment (EDGE), an ambitious new integrated development environment (IDE) and growing family of development tools based on the Eclipse Platform. EDGE IDE (formerly Nucleus EDGE) adds true embedded tools to the open and extensible Eclipse framework to provide the environment embedded developers have been waiting for.

When a software developer is acquiring a compiler, a primary consideration is the code quality produced by the compiler. But other features that are not required by the ANSI language description (that are tailored to embedded developer needs) can make the developer's task simpler to maintain. This paper investigates some desirable features of compilers used in embedded application development, and some techniques for making use of these features.

Hardware performance features available for embedded software to exploit are reviewed, including both recent advances as well as past trends. Hardware performance depends on clock speed and a large and still growing bag of tricks to discover and exploit concurrency in the problem being solved. The embedded software designer should be aware of the underlying hardware performance features in order to make the best design decisions. In particular, the recent advances in SIMD instruction sets, hardware multi-threading and single chip, multicore processors require explicit measures to exploit them in software.

This paper describes a methodology and possible implementations and applications for doing remote post-mortem debugging of an embedded RTOS application using crash dumps. The methodologies described can also be applied to other debugging scenarios, i.e. not crash-related post-mortem debugging, but in situations where other erroneous or undefined behavior occurs.

Debugging optimized code has been a topic of interest in academic as well as in industrial circles for a long time. Even after putting a lot of effort into this field, there is much to be done. The paper discusses the various problems encountered while debugging optimized code and tries to classify those problems.

In the race to manufacture embedded devices that run longer on a single battery charge, power optimization has become a major requirement in embedded tools. This elusive pot of gold has many hypotheses and theories in achieving acceptable savings. This paper talks about what factors affect optimizations, popular software power optimization schemes and also brings to light one of the potential applications of Fine-Grained Allocation (FGA) technology. Many compilers solely optimize code very early in the game, but fine-grained allocation allows more optimization at link time in addition to compiler optimizations! This technique empowers the developer to handcraft a complete executable according to unique embedded application needs.

Historically, linkers have been regarded as fairly simple tools. Their main functionality is to combine objects together, determine the layout of the final image, and resolve external symbols. This paper describes a basic model of the linking process and examines some shortcomings in this model. The powerful features of linkers are also described.

This document discusses runtime checks for C applications with special regard to the requirements of embedded systems development.

Runtime checks are features provided by a C/C++ compiler and/or a C-Runtime Library to help the developer track down problems at the source code line level. Runtime checks are performed when the program is executed. Runtime checks should not be confused with static checks or analysis, which is performed at compilation time. The checks and analysis performed by a C/C++ compiler are a valid help in development, but they are not capable of solving the more complex, hidden problems which can be easily introduced during an application?s implementation and coding phase.

This paper describes extended uses for JTAG Probes in the development life cycle of embedded systems.

Profiling can be a complex and unwieldy tool to use in the software development process. Using a well-formed and organized approach can have a significant effect on the outcome of profiling activities. This text will discuss the merits of using such an approach and continue discussing general ways to approach the task of profiling as both a means to optimize and debug a software solution. With the concepts presented in hand, the developer should be better prepared to use a profiling tool efficiently and successfully.

Embedded developers are more knowledgeable about their compiler tools than any other kind of developer. But those tools are usually little more than thinly adapted desktop technology. New compiler technology from Mentor Graphics decouples the layout of a program in memory from the organization of the sources, freeing embedded developers to place their code optimally in memory while maintaining the logical structure of the source base and enabling them to port compiled code to a new board, even when the source is unavailable.

The EDGE C/C++ Compiler tool kit introduces a new technology, Dynamic Variant Support (DVS, pronounced "devious") that describes processor variants via XML files. The result is a new variant can be supported in hours or days via an emailed text/XML file. No need to receive and install a large binary distribution.

This paper explores the difficulty of testing embedded software applications that operate in networked environments and distributed configurations. It then describes several innovations in software development tools - including full system simulation, application-aware and automated debugging, and application profiling - that help developers address these challenges.

What the heck is a codelet you ask? Simply put, a codelet is a script that runs in the EDGE Debugger. But much more than that, codelets are a technology in EDGE that allow you to get inside of your target in ways that simply are not possible in other debuggers. I believe that the hallmark of a truly great technology is that it can be used in ways that the designers never envisioned. Codelets are a technology like this: open ended, your imagination is the limit.

Recent history attests to the need for improved software testing methods in the automotive industry. Take, for example, Toyota?s October 2005 recall of 75,000 Prius hybrids in North America. A logic error in embedded software exacted a huge, if undisclosed, financial cost for the company and an inestimable cost in consumer confidence. And while we may never know the exact series of events that led to flawed code being shipped in the Prius, we do know the key to delivering bug-free software: test early and test often.

However, the distributed nature of automotive control systems, as well as the nature of the embedded software development process itself, makes testing a challenge. In the first place, simply gaining access to the necessary hardware environment for early and frequent testing may be expensive or impracticable. Moreover, effective validation and testing of distributed applications requires a sophisticated software infrastructure that is unlikely to be available off the shelf for the wide variety of microprocessors and peripheral hardware used in automotive systems and inordinately time-consuming and expensive to develop in-house. These factors speak to the need for testing environments that are abstracted from the underlying hardware architecture, capable of advanced regression testing and debugging of distributed applications, and aware of the operating system and protocol standards used in the automotive industry.

As the name suggests, virtual memory creates the illusion of an unlimited amount of memory. It allows multiple processes with memory needs larger than the physical memory to run simultaneously. This paper offers a high-level discussion on virtual memory. Topics to be discussed include implementation of virtual memory, advantages of using virtual memory, and the design of virtual memory.

This paper provides a high-level introduction into the real-time streaming protocol and its many use cases. It highlights the volatile nature of IP networks and gives insight into how RTP/RTSP enables a smooth transport across this dynamic terrain. In addition, the paper explores various implementations scenarios of multimedia applications while providing specific Nucleus RTP/RTSP features and services.

The mandate for certified safe and secure software was once the exclusive domain of military, medical and government. However, new regulations now play a critical role in the viability of devices manufactured for the global market. Security concerns have expanded to include devices that never before needed safe or secure functionality as a critical component for operation. This session examines today’s landscape. It looks at the natural evolution of technology, and its effects on today’s manufacturers. It will touch on national and cultural usage of standards as barriers to trade and government regulation. It discusses potential legal ramifications of the Sarbanes-Oxley act and others as they apply to corporate behavior, client data, information, and privacy.

This paper explores software abstraction concepts, discusses the costs associated with designing and implementing good levels of abstraction, and focuses on the usefulness of software abstraction within embedded systems.

This paper discusses why some of today's most common aerospace companies struggle when seeking commercial off-the-shelf software (COTS) to use in DO-178B applications. Combining knowledge from various perspectives including certification authorities, consultants, and users, this paper offers insight on how companies can address these costly issues to improve their bottom line and reap the many benefits when working with the DO-178B application.

All one has to do is to look to the media to determine that multicore is the hottest trend in the embedded space today. Multicore is challenging Linux for word count for the first time since Linux announced it was suitable for deployment in embedded devices. Every large semiconductor vendor has their own offering. New vendors have sprung up with their multicore architecture offerings. The question is: why are embedded device manufacturers becoming so enamored with multicore devices? This paper explores the factors driving vendors to multicore architectures and discusses the advantages of multicore development.

The OMAP architecture from Texas Instruments leads the way toward a dual-core computing paradigm for a world of ubiquitous information. The combination of a DSP and RISC unit on one chip provides a basis for the development of all kinds of devices that need to process digital signals while they run conventional code in parallel, especially when power is limited. Next-generation handsets are a convenient example of this approach, where a DSP handles the repetitive processing demands of voice and media streams while control and conventional application code runs concurrently on the RISC core. But the usefulness of the multi-core, system-on-a-chip idea goes much further.

This class explains the certification process using the RTCA/DO-178B standard as an example and the steps required to produce software that is certifiable under RTCA/DO-178B. In particular the requirements for documentation, testing, code-coverage and modified conditional decision coverage, requirements traceability and other aspects of RTCA/DO-178B compliance are discussed. This requirement for software certification will increase as more and more software-based systems become critical in our society. For example, developers of medical systems should note that the FDA is becoming increasingly stringent in certifying medical systems and associated software, as high-level FAA personnel have transferred to the FDA, hence gradually enforcing certification standards similar to those used by the FAA. Consequently, any developer with a need for RTCA/DO-178B certification and those with a need for software built to the highest level of safety and reliability will benefit from understanding the effort required to meet certification requirements.

Moving to C++ presents opportunities for higher programmer productivity. The requirements of embedded systems, however, demand that the adoption of C++ be carefully measured for the performance impact of run-time costs present in C++, but not in C.This talk suggests strategies for developers who are starting their acquaintance with C++.

A Look at the Impact of C++ on Efficiency and Optimization Techniques that Eliminate Unnecessary Overhead

C++ has rapidly gained in popularity in recent years and has clearly established itself as the next generation programming language. With C already in widespread use amond embedded and real-time software developers, it is hardly surprising that many of these same developers are turning to C++ for their next projects.

The use of FPGAs is growing in embedded designs and the embedded systems software market must continue to change to support this shift. With the added flexibility of the FPGA-based design, the embedded software solution, specifically the RTOS (Real Time Operating System), middleware, and drivers should complement the benefits of the FPGA. The RTOS should be well designed and easy-to-use, with the necessary and sufficient offering of middleware stacks and drivers. In addition to this prerequisite, the RTOS should also maintain the characteristics related to embedded designs, namely small code size, low interrupt latency, and full services needed for your application.

In a world that demands information distribution in a quick, seamless manner, IP Multicasting has stood out as a method of providing data to a large number of hosts without generating proportionally large traffic loads on network infrastructures. IP Multicasting utilizes Internet Group Management Protocol (IGMP) to send information to select hosts only. Nucleus NET supports IGMPv1 level 2. This is the highest level of support for IGMPv1. Setting up an application to use multicasting can seem daunting, but it becomes a simple task when broken down into initialization, receiving and transmitting.

Spring Quarter Newsletter
The primary focus of this quarter's newsletter is "Bring in the Pros: When to Use a Commercial RTOS". Other articles include: Security, IP Multicasting, Universal Serial Bus (Nucleus USB), and the release of our new evaluation center on ALL_ACCESS.

DHCP has become a common means of network administration. DHCP is to networking what Plug and Play is to PCI devices. It allows network administrators to control configuration options remotely and allows end users to move their network devices around subnets without needing to know the intricacies of the network topology.

Nucleus USB is a component of Nucleus Real-time Software that adheres to the USB specification (www.usb.org). It brings USB's many benefits including ease-of-use and plug-n-play advantages to Nucleus-based embedded systems. Nucleus USB allows developers to quickly incorporate USB into their systems with surprisingly little programming effort.

While developing the IPv6 protocol, the IETF (Internet Engineering Task Force) also designed and released specifications for a security architecture termed IPsec (IP Security). This architecture is a mandatory component of the IPv6 specification, which attempts to address the essential security needs of future network infrastructures. However, since IPv4 is currently the most widely deployed and mainstream protocol for today's networks, IPsec specifications for IPv4 have also been released to meet the ever-increasing security requirements.

Today's devices are increasingly based on multiprocessor designs. Systems-on-a-chip (SOCs) often contain two or more processor cores in homogeneous or heterogeneous combinations, and FPGA-based designs can include a virtually unlimited number and variety of cores. An interprocessor communications (IPC) mechanism is a common need when developing software for multicore systems. Nucleus IPC provides fast, efficient and deterministic interprocessor communications between processors running the Nucleus real-time operating system.

Networking has become an essential part of our lives. Networks of all types and sizes are in existence today. There are home networks that connect as few as two people and then there are networks of multinational organizations, which span the globe. Desktops, cell phones, automobiles and the equipment in our kitchen form a part of the diverse networked community. There is only one common thing about all networks: their operation is critical to its users.

There are increasing needs for embedded systems to provide large amounts of off-line data storage as desktop systems for future analysis and continued operation of the system. Traditionally, these requirements have been met by creating a proprietary file system or recreating a file system that is compatible with a standard format. In creating a proprietary file system, the results are often not portable and only serve limited use. In recreating a file system that is compatible with a standard format, the effort is so great that either compatibility is not achieved or only limited capabilities are available. Therefore, to support these requirements, Mentor provides Nucleus FILE, which is a full-featured, high performance and standard-compliant file system for embedded systems.

This white paper introduces the Nucleus USB Ethernet Communication class driver. Nucleus USB Ethernet Communication class driver has support for both host and function. Nucleus USB Host Ethernet Communication class driver can be used as an embedded host class driver to support Ethernet communication devices with the Nucleus USB Host stack. Nucleus USB Function Ethernet Communication class driver can be used as an embedded function class driver to create USB Ethernet peripherals with the Nucleus USB Function stack.

USB is the de facto standard for interconnectivity between PCs and external devices, and USB support for peripheral devices has been a part of embedded software since the beginning. Many embedded systems also host their own USB peripherals. Now, more and more embedded systems act as both host and function with USB On-the-Go (OTG) technology. The Nucleus USB product family includes USB Host, Function and OTG protocol stacks, hardware controller drivers and a long list of application-specific class drivers, integrated with the Nucleus Real-Time Operating System (RTOS) to immediately provide USB connectivity and a direct path to USB certification.

This white paper introduces the Nucleus USB Printer class driver. Nucleus USB Printer class driver has support for both host and function. Nucleus USB Host Printer class driver can be used as an embedded host class driver to support conventional printers with the Nucleus USB Host stack. It can also be used as an embedded function class driver to create USB printer peripherals with the Nucleus USB Function stack.

This white paper introduces the Nucleus USB to RS232 Adapter class driver. Nucleus USB RS232 Adapter class driver is used as an embedded host class driver to support the USB to RS232 adapter, e.g. FT232/FT245 device from Future Technology Devices International Ltd., with the Nucleus USB Host stack.

PPP (Point-to-Point Protocol) provides a standard method for transporting multi-protocol datagrams over point-to-point links. In the context of a Nucleus network application, PPP allows IP datagrams to be exchanged with a node at the other end of a point-to-point link. Typically, a client will initiate a PPP connection by using a modem to dial into a foreign server through the public telephone system. However, PPP is also used in environments where the physical medium is not always point-to-point. One such example is Ethernet. The PPPoE and L2TP protocols enable support for transmission of PPP packets over Ethernet.

A number of surveys conducted reflect the growing importance of information security to organizations. More than 1,400 organizations in 66 countries were surveyed in the Global Information Security Survey 2003 (conducted by Ernst & Young). Ninety percent of those surveyed considered IT security to be of high importance. Nucleus Cipher Suite (NCS) is a security library that bundles together a rich set of authentication and encryption algorithms. It is highly configurable and an ideal starting point for any security application.

The IPv4 protocol was not designed for the purpose it serves today. As the scope of the Internet grew, the IPv4 protocol attempted to grow with it, but finally, it has reached its limits. With the eminent exhaustion of the IPv4 address space and a mounting number of embedded devices pushing the limits of the current infrastructure, the need for a new Internet protocol is urgent. The constraints of the IPv4 protocol have restricted innovation in the embedded industry, but the improvements introduced by IPv6 will progress the embedded industry by adding TCP/IP capability to devices never previously imagined. This paper aims to outline the rise and fall of the IPv4 protocol, the advantages of IPv6 in the embedded industry and the mechanisms in place to transition from IPv4 to IPv6.

This white paper will walk you through the history of Nucleus NET and why, in particular, it is so much a part of our future. We will also detail some of the features that we believe make Nucleus NET a formidable challenge to other embedded TCP/IP stacks.

The requirements for file storage on portable devices are driven by interoperability and reliability in a battery powered environment. Portable devices typically share data with external systems such as a desktop computer in a standardized format. Power loss or surge while accessing a storage device poses a significant risk of corrupting file system data. This paper will discuss the file system requirements of portable devices along with suggesting strategies for meeting the design requirements.

The focus of this technical paper is on how the Nucleus OS Security Services can be used to exploit the encryption hardware available on the PPC8349E to achieve significant performance increases. This paper is part of the Nucleus OS Security Services reference platform that is also available on this website. The evaluation platform provides a complete system for utilizing and evaluating the performance of the MD4, MD5, SHA-1, SHA-256, DES, 3DES, CAST-128, Blowfish, and AES encryption algorithms using either pure software or hardware acceleration.

The Nucleus OS can significantly improve the performance, response times and memory system utilization in many complex systems, where other bulkier OS choices add significant overhead and do not provide real-time response.  This paper discusses how the smaller footprint of Nucleus and its real-time capabilities can address improved resource utilization to optimize PPE and SPE interaction.

This white paper discusses the features of Texas Instruments' DaVinci platform and how Mentor Graphics provides a complete solution to support this platform. This solution includes a discussion on the EDGE developer Suite, Nucleus OS, and Inflexion Platform UI. This paper further delves into how the DaVinci platform can be used in different multimedia based devices and provides an example to work through the details.

Exciting times these are! The automotive technology industry is seeing a whole new trend taking shape. Car technology is just in its infancy and already there are many interesting concepts being rolled out from major car manufacturers all over the world. There have been early successes and minor setbacks in this highly competitive industry. This paper will attempt to outline some of the advances that have been made recently, and based upon past trends, will predict the direction this industry is going. In the mind of the author, this direction holds enormous potential for new applications of embedded technology, can bring a wave of new trends and mega-trends in the automobile industry, accounts for many years of sustained fruitful business for car manufacturers and increases value and functionality. It also decreases costs with every coming year for the person who matters the most: the car buyer.

Tokyo, Detroit and Munich, the race is on!

Many types of embedded software are driven by performance. Increasing performance of the software can lead to savings by requiring less CPU horsepower to run the application, thus enabling more functionality to be added, or by allowing the application to be possible at all. In the following article, I will show three techniques that have been valuable in measuring and increasing embedded software performance learned through my firsthand embedded experience.

Multicore systems are on the advent. With the changing of hardware, software also needs to be changed and updated. This article deals with issues faced while developing, porting and debugging software for multicore systems.

This technical paper provides an overview of Nucleus I2C product line. It discusses the benefits of the inter IC communication (I2C or IIC or I2C) protocol, its applications and its requirements. It also describes the products included in the Nucleus I2C product line along with their requirements.

This technical paper provides an overview of the Nucleus SPI product line. It discusses the benefits of Serial Peripheral Interface (SPI) bus, its applications and its requirements and describes the products included in the Nucleus SPI product line along with their requirements.

Telematics is the combination of computing, wireless telecommunication and information technology to provide the capability to effectively convey information over a network to improve government business and consumer services. In the future, telematics will be a base technology for ubiquitous life, in the field of automotive telematics, home/personal telematics and servicing medical care and health to users. This paper provides an overview of telematics and components used in telematics products.

Explore the use of a simple processor communication method in an embedded system. The embedded system evaluated deploys multiple microprocessors where one or more microprocessors are viewed as slave devices. Specific implementation involves a master/slave multi-processor embedded system. The master device consists of an application residing in an embedded operating system environment. The slave devices consist of a microprocessor with a single processing thread. The goal is to provide a robust, yet simple method of communications between the two microprocessor devices. The communication method should be extendable to include a single master communicating with multiple slave devices. The discussion of this paper will include some problems that may be encountered and potential solutions.

The IPv4 protocol was not designed for the purpose it serves today. As the scope of the Internet grew, the IPv4 protocol attempted to grow with it, but finally, it has reached its limits. With the eminent exhaustion of the IPv4 address space and a mounting number of embedded devices pushing the limits of the current infrastructure, the need for a new Internet protocol is urgent. The constraints of the IPv4 protocol have restricted innovation in the embedded industry, but the improvements introduced by IPv6 will progress the embedded industry by adding TCP/IP capability to devices never previously imagined. This paper aims to outline the rise and fall of the IPv4 protocol, the advantages of IPv6 in the embedded industry and the mechanisms in place to transition from IPv4 to IPv6.

There are traditionally two reasons to program in assembler: performance and hardware control. Modern hardware and compilers have massively reduced the range of situations in which the performance reason applies. Conversely, the issue of hardware control remains paramount in embedded applications. We discuss how programmers tackle the issue and offer a technique, dubbed "Register'd C," that is a sublimate of best practices as gleamed by observing the most efficient embedded programmers in action.

This paper examines issues related to shared resources in a multi-tasking system, and how to protect these resources from being corrupted. Semaphores and the different ways they can be used are discussed in detail. The priority inversion and deadlock problems that can arise when using semaphores are explained, and solutions to work around the problems are provided.

Embedded technology in some form or fashion has been used to make improvements in nearly every field of study from law enforcement to medicine to aerospace engineering. The embedded hardware and software systems used to facilitate such improvements are complex. In the medical field alone, many devices use these systems to control vital sign monitors, defibrillators, lasers, and other high-precision instruments. Many of these new devices are managed by a real-time operating system (RTOS). The RTOS ensures that all time critical events get handled as efficiently as possible by using real-time software that manages the timing of a microprocessor. An RTOS may also help simplify the design process by allowing the system to be separated into many autonomous entities. However, the implementation and debugging of the tasks' data content, communication, synchronization, etc., remain quite complex. Reliability, time, size, precision, and cost are all factors that must be considered during the development of an RTOS or other embedded software for the medical field. This is especially true of the vision care division. Developers concerned with vision care need tools and an integrated development environment (IDE) that allow them to focus directly on the product being designed throughout the entire development process from beginning to end.

USB is ubiquitous on PCs and peripherals, but this was not always the case. Let's take a stroll down memory lane to see where USB has been, what it can do, and where it is going. This paper provides an overview of USB and the direction USB is currently moving for future development.

This paper provides details on booting from flash with MMU or images with non-contiguous memory.

Programmers new to the field of embedded network programming usually hail from a Windows or UNIX background. Since a desktop computer has virtually unlimited resources and processing power, network programming varies greatly in an embedded system with limited resources and a specialized operating system. Although an embedded TCP/IP stack should operate to some level of success under poor programming conditions, an informed and cautious programmer can make optimal use of system resources and, therefore, write a better application. This paper aims to outline ways to program efficiently and defensively in an embedded system to create application tasks, conserve resources, maximize CPU cycles, and optimally configure the node.

This paper discusses the communication mechanisms needed for most multicore systems. It examines the common use cases that are needed, what the communication mechanism should support, how it should be implemented, and problems that may arise.

This paper provides debugging tools and tips to embedded software engineers. Various hardware and software tool options that have proven helpful over time are discussed. By using these readily available options, you will be able to save time with getting your project designed, debugged, and developed on or before your deadline.

This technical paper provides an overview of Nucleus POS, a demonstration for point of sale outlets. It presents the trends in the point of sale solutions and describes the features of the Nucleus product line that match the requirements of retail automation, especially the point of sale industry. Finally, the architecture of the Nucleus products employed in Nucleus POS are outlined, together with some of the features and benefits.

This paper presents how a serial device driver was redesigned using software abstraction via a series of steps. Proper abstraction leads to benefits in more efficient porting, testing, and code reuse. Device drivers are commonly written without sufficient thought given to the work required to create future ports, for testing and code reuse.

Memory loss is a persistent and pernicious threat in embedded systems. However, it can be prevented with comprehensive diligence in design, development and testing. This paper provides an overview for managing memory loss in embedded systems.

This paper examines the embedded technology behind smart homes and the communication systems they contain. It also explains the many benefits of owning a smart home in particular for the disabled and the elderly. The benefits described include convenience, security, and economy.

In some ways, writing embedded software is much like writing software for any other kind of application. But in other ways, it differs widely. This means that embedded software developers can learn lessons from their desktop-bound counterparts, but they must harvest that wisdom selectively. Embedded software technology appears to lag behind - it's often a little late picking up on new trends and fashions. That's largely because embedded developers have a cautious, conservative attitude, which is borne out of years of experience contending with limited resources: memory that can't be treated as unlimited and CPUs that are powerful enough, but only just.

The choice of programming language echoes this pragmatic conservatism perfectly. Embedded guys were slow to pick up on high-level languages years ago, but eventually C became accepted. It took the arrival of very high quality code generation and transparent debugging for the industry to accept such new-fangled ideas, and that was only under the relentless pressure to become more productive. The obvious step on from C is C++. Even though its use for embedded software has steadily increased in recent years, it is far from universal. Why is that?

This paper provides a technical description of the Nucleus MTP product, including its feature set and functionality. A technical fact sheet provides key capabilities and requirements of Nucleus MTP for creating MTP-compliant function peripheral devices.

This technical paper provides a description of the IEEE 802.1X network access standard for wired and wireless Ethernet networks. Details are given on Nucleus 802.1X SUP, an implementation of this standard. Information is provided as to what features are included in the Nucleus solution, how it works and how it fits in to the Nucleus RTOS.

This technical paper provides the background for the Nucleus FILE product line. It describes the product architecture and components overview.

This technical paper provides a description of the IEEE 802.11i enhanced security standard for wireless Ethernet networks. Details are given on Nucleus 802.11i, an implementation of this standard, information is provided as to what features are included in the Nucleus solution, how it works and how it fits in to the Nucleus RTOS.

Nucleus GRAFIX is Mentor Graphics' product for creating graphics user interfaces and is specifically designed for embedded systems. We've taken advantage of Nucleus PLUS to combine multitasking technology with a detailed understanding of graphics hardware to harness unique capabilities that make Nucleus GRAFIX exceptionally fast!

Nucleus GRAFIX supports modern metaphors such as windows, text boxes, buttons, fonts and other controls that allow you to create professional desktop style interfaces. Mentor Graphics also recognizes that desktop interfaces do not always work in the embedded world, therefore, Nucleus GRAFIX scales to fit your system allowing you to create a completely custom interface to match the embedded nature of your system.

Nucleus GRAFIX is a portable, full-featured graphics toolkit that contains three valuable parts: Windowing Toolkit for a high-level way to build your interface; Rendering Services for low-level drawing; and device drivers that are highly portable across multiple CPUs and graphics hardware. Many commercial LCD and VGA displays and input devices including touch screen, mouse and keyboard are supported. You can design your GUI using the Microsoft® Visual Studio® software to produce a resource script that is read and converted to C for ultimate integration into your application.

This technical paper focuses on the market drivers, audio formats and standards for mobile phones that require ring tones, music playback, game soundtracks, and system audio controls required for the mobile audio applications.

This technical paper provides an overview to the Nucleus uiPLUS product concerning its components and functionality.

This technical paper provides an overview of Accelerated Technology’s terminal application solution. It surveys the origins and uses of shell programs, and describes the implementation of Nucleus SHELL. The architecture of the product is outlined, together with some of the features and benefits.

This technical paper provides an overview of Nucleus PCI. It surveys the origins of PCI, and describes its specifications, general requirements and its compatibility with other Nucleus products available from Accelerated Technology.

This paper provides a description of Nucleus POSIX, Nucleus POSIX file system (FS), Nucleus POSIX AIO (Asynchronous I/O), Nucleus POSIX networking and Nucleus POSIX RTL (Runtime Library). This paper discusses the supported functionality and general requirements of Nucleus POSIX for writing embedded applications.

This paper provides a description of the Nucleus USB Host Power class driver, a subclass of the Human Interface Device (HID) class of USB devices. This paper discusses the architecture, supported functionality and general requirements of the Nucleus USB Host Powerclass driver.

This technical paper provides a description of the Nucleus PCI-X, an extension of Nucleus PCI. It surveys the origins and uses of PCI-X, and describes its specifications, general requirements and its compatibility with other Nucleus products available from Accelerated Technology.

This technical paper provides an overview of Accelerated Technology's CAN solution. It surveys the origins and uses of Controller Area Network, and describes the implementation of the CAN standard available from Accelerated Technology. The architecture of the product is outlined, together with some of the features and benefits.

This technical paper provides a survey of the background of Nucleus Dynamic Download. It explains the origins of embedded systems and describes the implementation of Dynamic Download capabilities and product integrations available from Accelerated Technology. The architecture of the product is outlined together with some of the features and benefits.