Courses by Design Area
Electrical & Wire Harness Design
- Capital Analysis Core
- Capital Analysis Modeling
- Capital Capture
- Capital Desktop Architect
- Capital Engineer 1
- Capital Engineer 2
- Capital FormBoard XC
- Capital Harness XC
- Capital Integrator XC
- Capital Labor Costing
- Capital Library
- Capital Library Live Online
- Capital Logic Aero
- Capital Logic Generative
- Capital Logic Generative Live Online
- Capital Logic Interactive
- Capital Logic Interactive Live Online
- Capital Material Costing
- Capital Modular XC (Functional and Production)
- Capital Modular XC (Functional)
- Capital Modular XC (Production)
- Capital Oracle System Administration
- Capital Systems Administration
- Capital Topology
- VeSys 2.0 Design
- VeSys 2.0 Design Live Online
- VeSys 2.0 Harness
- VeSys 2.0 Harness Live Online
Embedded Software
ESL
FPGA
- ADiT for Fast-SPICE Simulation
- Artist Link
- Board Station RE
- C++ for Hardware Design
- CES for Board Station Flow
- CES for Expedition PCB
- Design Architect
- Design Architect/Library Management System
- DO-254 Compliance Overview
- DO-254 Compliance Overview Live Online
- DxDesigner for Expedition PCB Flow
- Eldo Simulation
- Expedition PCB Flow: Automation and Scripting
- HDL Designer Series
- HDL Designer Series Live Online
- I/O Designer
- IC Station - Accelerating Your Productivity
- IC Station With ICstudio
- ModelSim Advanced Topics
- ModelSim HDL Simulation
- Precision Synthesis: FPGA Design
- Questa ADMS for A/MS Design Verification
- Questa Clock Domain Crossing Verification
- Questa Essentials
- Questa Formal Verification
- ReqTracer for FPGA/ASIC Design Assurance
- Signal Integrity and High Speed Methodology
- SystemVerilog for Verification
- VHDL Introduction
- VHDL-AMS (3 Day)
Functional Verification
- ADiT for Fast-SPICE Simulation
- Artist Link
- C++ for Hardware Design
- Certe OVM Testbench
- Certe OVM Testbench Live Online
- Eldo Simulation
- FormalPro
- HDL Designer Series
- ModelSim Advanced Topics
- ModelSim Advanced Topics Live Online
- ModelSim HDL Simulation
- ModelSim HDL Simulation Live Online
- OVM to UVM Transition
- OVM to UVM Transition Live Online
- Perl for EDA
- PSL: Assertion Based Verification with Questa
- PSL: Assertion Based Verification with Questa Live Online
- Questa ADMS for A/MS Design Verification
- Questa Clock Domain Crossing Verification
- Questa Essentials
- Questa Essentials Live Online
- Questa Formal Verification
- Signal Integrity and High Speed Methodology
- SystemVerilog Assertions
- SystemVerilog Assertions Live Online
- SystemVerilog for Verification
- SystemVerilog for Verification Live Online
- SystemVerilog Open Verification Methodology
- SystemVerilog Open Verification Methodology Advanced
- SystemVerilog Open Verification Methodology Live Online
- SystemVerilog Universal Verification Methodology
- SystemVerilog Universal Verification Methodology Advanced
- SystemVerilog Universal Verification Methodology Live Online
- Tessent Scan and ATPG
- Verilog Fundamentals for SystemVerilog
- Verilog Fundamentals for SystemVerilog Live Online
- Verilog Introduction
- VHDL Advanced
- VHDL Introduction
- VHDL-AMS (3 Day)
- Visual Elite
IC Design
- ADiT for Fast-SPICE Simulation
- Artist Link
- Calibre Advanced Topics: Mastering Calibre eqDRC
- Calibre Advanced Topics: Mastering Calibre eqDRC Live Online
- Calibre Advanced Topics: nmLVS Debug Case Studies
- Calibre Advanced Topics: nmLVS Debug Case Studies Live Online
- Calibre Advanced Topics: Writing PERC Rules
- Calibre Advanced Topics: Writing PERC Rules Live Online
- Calibre Dense RET
- Calibre Dense RET: nmOPC
- Calibre DRC Optimization
- Calibre DRC Optimization Live Online
- Calibre Fundamentals: DESIGNrev
- Calibre Fundamentals: DESIGNrev Live Online
- Calibre Fundamentals: DFM Case Studies
- Calibre Fundamentals: DFM Case Studies Live Online
- Calibre Fundamentals: Performing DRC/LVS
- Calibre Fundamentals: Performing DRC/LVS Live Online
- Calibre Fundamentals: Working with PERC
- Calibre Fundamentals: Working with PERC Live Online
- Calibre Fundamentals: Writing DRC/LVS Rules
- Calibre Fundamentals: Writing DRC/LVS Rules Live Online
- Calibre RET
- Calibre TVF
- Calibre TVF Live Online
- Calibre xRC Parasitic Extraction
- Calibre xRC Parasitic Extraction Live Online
- Eldo Basic Simulation
- Eldo Simulation
- HyperLynx Analog
- IC Design Flow With ICstudio
- IC Station - Accelerating Your Productivity
- IC Station With ICstudio
- Olympus-SoC
- PSL: Assertion Based Verification with Questa
- Questa ADMS for A/MS Design Verification
- VHDL-AMS (3 Day)
- VHDL-AMS (5 Day)
Intellectual Property
Mechanical Analysis
PCB Design Software & Tools
- AMPLE
- Analog Designer Analog Simulation
- Board Station Comprehensive
- Board Station RE
- Board Station RE Live Online
- Board Station XE
- CES for Board Station Flow
- CES for Board Station XE Flow
- CES for Expedition PCB
- CES for Expedition PCB Live Online
- Design Architect
- Design Architect Live Online
- Design Architect/Library Management System
- Design Capture for Expedition PCB Layout
- Design Capture to Expedition PCB Process
- DxDesigner for Expedition PCB Flow
- DxDesigner for Expedition PCB Flow Live Online
- DxDesigner for PADS Flow
- DxDesigner for PADS Flow Live Online
- Expedition PCB Advanced
- Expedition PCB Advanced Live Online
- Expedition PCB Flow: Automation and Scripting
- Expedition PCB Flow: Automation and Scripting Live Online
- Expedition PCB Introduction
- Expedition PCB Introduction Live Online
- HyperLynx Advanced High-Speed PCB Analysis
- HyperLynx Advanced High-Speed PCB Analysis Live Online
- HyperLynx Analog
- HyperLynx Analog Live Online
- HyperLynx Power Integrity Analysis
- HyperLynx Power Integrity Analysis Live Online
- HyperLynx Signal Integrity Analysis
- HyperLynx Signal Integrity Analysis Live Online
- I/O Designer
- I/O Designer Live Online
- Library Manager for Design Capture to Expedition PCB
- Library Manager for DxDesigner to Expedition PCB Flow
- Library Manager for DxDesigner to Expedition PCB Flow Live Online
- PADS Layout
- PADS Layout Live Online
- PADS Logic
- PADS Logic Live Online
- PADS Router
- PADS Router Live Online
- RF Design in DxD/Expedition
- RF Design in DxD/Expedition Live Online
- Signal Integrity & EMC Pro Tune-Up
- Signal Integrity & EMC Process
- Signal Integrity and High Speed Methodology
- vSure Introduction
Silicon Test and Yield Analysis
- Tessent Diagnosis
- Tessent Diagnosis Live Online
- Tessent MemoryBIST
- Tessent MemoryBIST and LogicBIST
- Tessent MemoryBIST and LogicBIST Live Online
- Tessent MemoryBIST Live Online
- Tessent Scan and ATPG
- Tessent Scan and ATPG Live Online
- Tessent TestKompress and Advanced Topics
- Tessent TestKompress and Advanced Topics Live Online