Design-for-Test: Scan and ATPG
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| Date Begins | Date Ends | Time | Location | Register |
|---|---|---|---|---|
| Aug 05, 2009 | Aug 07, 2009 | 9:00am - 5:00pm | San Jose, CA | Register |
| Aug 25, 2009 | Aug 28, 2009 | 9:00am - 5:00pm | Austin, TX | Register |
| Oct 27, 2009 | Oct 30, 2009 | 9:00am - 5:00pm | Tempe, AZ | Register |
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Duration: 4 Days
Pricing: $3,200 USD
Course Part Number: 057857
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Course Overview
The Design-for-Test: Scan and ATPG course is designed to drive the development of skills and knowledge in scan and ATPG design processes utilizing Mentor Graphics tools: DFTAdvisor™, FastScan™, TestKompress®, MacroTest™, DFTVisualizer™, and ModelSim®.
This course teaches how to insert full scan in a design using the DFTAdvisor tool flow, and shows you how to create high quality test patterns using the traditional ATPG tool flow. This course also teaches traditional ATPG compression techniques along with industry-standard EDT compression techniques.
The hands-on labs are designed to reinforce key concepts through practical experience and to develop proficiency with Mentor Graphics Design-for-Test (DFT) tool suite under the guidance of industry-expert instructors.
You Will Learn How To
- Analyze ATPG messaging
- Achieve high test coverage
- Create high quality patterns
- Perform advanced test methodologies
- Troubleshoot areas of low test coverage
- Achieve high test pattern compression
- Troubleshoot DRC violations and simulation mismatches
- Use EDT to create compact pattern sets
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using DFT software. Hands-on lab topics include:
- Accessing documentation and getting help
- Using the scan and ATPG tool flow (with and without a design rule violation)
- Setting up new and existing scan pins (internal or external)
- Balancing scan chains with multiple clock domains
- Writing and editing scan chain order files and stitching
- Reading and analyzing messages
- Determining the cause of undetected faults
- Using common methodologies to attain a quick estimate of test coverage
- Creating and saving patterns in different formats
- Verifying patterns using ModelSim
- Reading ASCII files into FastScan
- Modifying timeplates
- Using traditional ATPG compression techniques
- Using basic EDT compression techniques
- Creating fault models and fault grading
- Using MacroTest and top-up ATPG
- Fault-grading boundary scan and top-up ATPG
- Troubleshooting areas of low test coverage
- Troubleshooting DRC violations and simulation mismatch-full tool flow
Prerequisites
- Experience with UNIX environments
- A basic background in DFT
Key Topics
- Basic scan concepts and DFT flow
- Accessing SupportNet information
- Design Rules Checking (DRC)
- Analyzing DRC violations
- Troubleshooting areas of low test coverage
- DFTVisualizer
- Test coverage reporting
- Creating FastScan pattern types
- Creating and optimizing patterns
- Black boxes
- Testing embedded memories
- Advanced test methodologies
- Top up ATPG
- Fault grading
- Fault classes
- Debugging bus contention
- Debugging simulation mismatches