DFT: TestKompress and Advanced Topics
- Add Courses
- Confirm Schedule
- Enter Contact Information
| Date Begins | Date Ends | Time | Location | Register |
|---|---|---|---|---|
| Aug 03, 2009 | Aug 04, 2009 | 9:00am - 5:00pm | San Jose, CA | Register |
| Sep 22, 2009 | Sep 23, 2009 | 9:00am - 5:00pm | Austin, TX | Register |
Don't see a date or location that works for you?
Request this class in your area
Duration: 2 Days
Pricing: $1,600 USD
Course Part Number: 221302
Contact us for details about training at your site
Course Overview
This course introduces Embedded Deterministic Test (EDT™) technology and TestKompress™ to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with smaller (< 130 nm) geometries. It is especially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size or application time are issues.
The hands-on labs are designed to reinforce key concepts through practical experience and to develop proficiency with the Mentor Graphics DFT tool suite under the guidance of our industry-expert instructors.
You Will Learn How To
- Access help and navigate documentation for TestKompress
- Use TestKompress in three different IP generation flows
- Perform EDT Automation with TestKompress
- Compare compression results
- Create TestKompress test patterns
- Troubleshoot common DRC violations
- Perform At-speed testing
- Simulate test patterns and troubleshoot mismatches
- Use TestKompress and Boundary Scan in the same flow
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using DFT TestKompress software. Hands-on lab topics include:
- Exploring TestKompress User Interface and Information Resources
- Integrating TestKompress into Gate-level, RTL-level, and Modular Design Flows
- Exploring TestKompress Logic Features and Options
- Understanding and Troubleshooting Common DRC Violations
- Determining Compression and Performance
- Using At-speed Testing
- Using TestKompress with Boundary Scan
- Graphically Viewing Data and Troubleshooting Common DRCs
Prerequisites
- A background in Design-for-Test
- Mentor Graphics Education Services training course, Design-For-Test: Scan and ATPG Training
Key Topics
- TestKompress Basics
- Pattern Simulation Mismatch Debugging
- Performance Analysis and Improvement
- TestKompress Hierarchical/Modular Design Flow
- Advanced Topics including AT Speed Testing, Clock Reuse, Multiple Fault Models, TestKompress, and Boundary Scan
- Graphically Analyzing Design and Test Data With DFTVisualizer