Precision Synthesis: FPGA Design

Course Part Number: 232343

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Course Overview

The Precision® Synthesis: FPGA Design course will help you understand how to use Precision Synthesis to synthesize your design from HDL RTL to technology specific gate-level netlist.

Hands-on lab exercises will reinforce lecture and discussion topics under the guidance of our industry expert instructors.

You Will Learn How To

• Create a design project using Precision Synthesis
• Manage design project data in Precision Synthesis
• Set up constraints to optimize your design
• Read timing reports and identify timing bottlenecks
• View the synthesized design results
• Create block based designs
• Use the command line and scripts
• Proceed to the vendor-specific P&R stage

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using the Precision Synthesis software. Hands-on lab topics include:

• Basic synthesis flow
• Setting Constraints
• Quality of Results Improvement
• Physically Aware Synthesis
• Black Box Flow
• Bottom-Up Flow
• Incremental Synthesis
• Resource Management

Prerequisites

• Familiarity with VHDL, Verilog, or SystemVerilog for RTL design
• Familiarity with concepts of RTL logic synthesis
• Familiarity with Windows operating systems

Key Topics