Questa Essentials

Course Part Number: 223971

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Course Overview

The Questa Essentials course will teach you the benefits of Questa’s advanced verification environment. Lectures include advanced functional verification topics such as constrained-random stimulus generation, functional coverage, code coverage, and SystemVerilog assertions.

Additional topics include viewing and debugging SystemVerilog class objects, Direct Programming Interface (DPI), Power Aware verification, and transactions. You will also learn how to use Questa’s integrated Verification Management technology, comprising of a verification plan, the Unified Coverage Database (UCDB), test tracking capabilities, ranked test results, and generated HTML reports.

Hands-on lab exercises will reinforce lecture and discussion topics under the guidance of our industry expert instructions.

You will learn how to

• Create a Verification Plan
• Perform “Code Coverage” on a design
• Debug SystemVerilog Assertions in the GUI
• Create constrained random simulation environments
• Debug conflicting constraints
• Create and save different verification runs in the UCDB
• View covergroups, assertions, and cover directives in the GUI
• Debug SystemVerilog Assertions in the Assertion Thread Viewer (ATV)
• Import a test plan into the Verification Management Test Browser
• View and track the Test Plan and regression tests in the Test Tracker window
• Merge regressions tests and rank them
• Find and fix unlinked test items in the Verification Plan
• Experiment with Questa’s advanced debugging capabilities
• Call a “C” function from SystemVerilog through DPI
• Use Questa’s Power Aware functionality using UPF
• Use commands to facilitate performance and debugging
• Create and record Verilog and SystemVerilog transactions
• View transactions in the GUI

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using Questa software. Hands-on lab topics include:

• The Verification Plan
• Code Coverage
• Debugging SystemVerilog Assertions
• Debugging a failure in the constraint solver
• Verification Management highlighting OVM methodology
• Debugging
• DPI
• Power Aware using UPF
• Vopt and performance
• Transactions

Prerequisites

• Familiarity with SystemVerilog class-based objects, constrained random, functional coverage, and assertions
• Familiarity with VHDL and Verilog

Key Topics

Related Courses

• ModelSim / Questa Core: Advanced Topics
• ModelSim / Questa Core: HDL Simulation
• SystemVerilog Assertions
• SystemVerilog for Verification
• SystemVerilog Open Verification Methodology
• Verilog Fundamentals for SystemVerilog
• Verilog Introduction