Duration: 4 Days
Pricing: $2,800 USD
Course Part Number: 230367
Contact us for details about training at your site Course Overview
This 4-day course is intended for designers who are new to Verilog and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis.
Detailed lab exercises help reinforce what is discussed during the lectures and provide you with extensive tool usage experience under the guidance of our industry expert instructors.
You will learn how to
- Avoid the common mistakes people make when first using Verilog
- Correctly use blocking and non-blocking assignments.
- Correctly model combinational and sequential hardware blocks
- Write synthesizable RTL design descriptions
- Structure and create testbenches to verify your RTL code
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using QuestaSim simulator. Hands-on lab topics include:
- Correct usage of functions and tasks
- How to describe bidirectional bus interfaces
- Code a synthesizable RTL State machine
Audience
Design and Verification Engineers interested in Verilog
Prerequisites
Familiarity with concepts of verification
