TAU Board Level Timing Analysis

 
 

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Duration:  2 Days
Pricing:  $1,400 USD
Course Part Number: 067808

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Course Overview

This course provides you with concepts and instruction on how to use the Tau toolset to create Symbolic Timing models and analyze timing of board-level designs using Symbolic Timing Analysis.
 

Objectives

  • Introduce the key concepts of timing analysis
  • Perform timing verification on synchronous and asynchronous subsystems of a complete design
  • View and fix timing violations
  • Estimate delays by importing placement files
  • Export routing constraints used to drive physical layout.
  • Create Tau design database from a netlist and an existing Tau library
  • Assign properties and learn about their functions
  • Create models from templates by importing component timing and functional information from external sources used in modeling
  • Create models from scratch using information from the component's datasheet 

Audience

This course is designed for engineers performing timing analysis of board-level designs.
 

Prerequisites

Students who attend this course should have some knowledge of timing analysis and printed circuit board design. The course may be taught in a UNIX or NT System environment and experience with these environments are assumed.
 

Key Topics

  • Introduction to Tau and key concepts
  • User Interface
  • Verifying Synchronous and Asynchronous Subsystems
  • Interconnect Analysis
  • Creating a Tau analysis databases
  • Creating Tau models
 
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