Duration: 2 Days
Pricing: $1,400 USD
Course Part Number: 213150
Contact us for details about training at your site Course Overview
The "ePlanner High Speed Design" course introduces the student to ePlanner's innovative method for design constraint development using pre-layout transmission line analysis, sweep analysis techniques, layout prototyping, constraint verification, procedures for passing constraints to a CAD system, and post-layout analysis and reporting. The course is designed with both lecture and hands-on exercises, allowing the student to try all key concepts.
You will learn how to
- Adopt ePlanner to provide a powerful and efficient constraint-driven design methodology
- Use Scratchpad to develop design Topology Templates using the Solution Space Exploration methodology
- Create topologies and evaluate sweep analysis results
- Create constraint classes and assign constraints within the Constraint Management System (CMS)
- Translate and create board and component outlines for Planview
- Perform signal integrity analysis using both Scratchpad and Planview
- Use Planview to define component placement and net from-to scheduling
- Perform PCB netlisting from the ePlanner environment to pass both design data and design constraints to various CAD systems
- Use ePlanner to display post-route signal integrity analysis results
- Use Scratchpad to perform analysis on post-route nets
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using ePlanner. Hands-on lab topics include:
- Applying Solution Space Exploration
- Sweep Analysis with Scratchpad
- Crosstalk Analysis with Scratchpad
- Creating Configurations, Constraints and Topology Templates
- Assigning Constraints in CMS
- Placement Prototyping with Planview
- Passing Constraints to CAD Systems
- Performing post-route signal integrity analysis
Audience
- Engineers and schematic designers who will use ePlanner to constrain their designs and perform signal integrity analysis prior to the layout phase
- System engineers responsible for developing design guidelines and constraints that will be applied across several designs within a system
- CAD Engineers and Managers who will be responsible for integration of ePlanner in their design flow
Prerequisites
Familiarity with Windows NT, 2000, XP or UNIX operating systems
Key Topics
Module 1- ePlanner Fundamentals
- Signal Quality Strategies
- Using SI Tools
- ePlanner Methodology: Interconnect Planning (ViewDraw Flow)
- ePlanner Methodology: Interconnect Planning (Cadence/Mentor DA Flow)
- The Domain of SI Analysis
- Types of Signal Integrity Problems
- Threshold Errors
- Multi-crossing Errors
- Delay Errors
- Signal Integrity Errors
- Ringback Errors
- Oscillation
- Circuit Electrical Requirements
- SI Report
- Crosstalk
Module 2 - Solution Space Exploration (SSE)
- Viewing Sweep Results
- Data Queries
- 2D Chart
- 3D Chart
- Sweepgen.cfg
- The Solution Space
- Design Constraints and Margin
Module 3 - Creating Topologies in Scratchpad
- ePD Installation Tips
- Environment Variables
- Dashboard
- ePD Projects
- Dashboard diagnostics
- Scratchpad
- Attribute Editor
- Multi-Attribute Editor
- Attribute Sweeps
- Attribute Reference, Operators and Functions
- Select and Map Functions
- Attribute Reference
- Random Sampling
- Drivers and Receivers
- Tlines
- Setup Layer and Width
- Xline Segments
- Board Stackup
- Terminal Voltages
- Creating Topologies
Module 4 - Scratchpad Analysis and Topology Templates
- Scratchpad Browser Window
- The Waveviewer
- Procedure: Selecting Waveforms from a Single Simulation
- Procedure: Selecting a Single Waveform from a Simulation
Module 5 - Advanced Methods with Scratchpad
- Methods of Specifying Models
- Simulation of Models
- quadlibs.lst
- Adding XTK Libraries
- Package Models vs. Pin Models
- Assigning Models
- Sweeping Models
- Using IBIS Specifications
- IBIS Translation Cache Inspector
- TOPSPEC
- Using Topspecs
- Abutment
- Analysis with Xlines
- Board Stackup and Materials
- Cross Section Editor
- CFED - Traces
- CFED - Layers
- XFX
- Crosstalk Waveforms
- Crosstalk Report
Module 6 - ePlanner Projects and Design Configurations
- ViewDraw Flow
- Design Architect Flow
- Concept Flow
- Schematic Preparation (ViewDraw)
- Schematic Preparation (Design Architect)
- Schematic Preparation (Concept)
- Workbench
- Workbench Browser
- What if the Design Changes?
- Shape Libraries
- Creating Board Outlines and Component Shapes
- Finding Shapes
- XTK Libraries
- XTK Models
Module 7 - Assigning Constraints in CMS and ViewDraw
- ePlanner Methodology: Interconnect Planning (ViewDraw Flow)
- ePlanner Methodology: Interconnect Planning (Cadence/Mentor DA Flow)
- workbench/CMS Data Flow
- Hierarchy of Constraints
- Class Instances
- The Constraint File (.cns)
- CMS Overview: Hierarchy
- Capturing Constraints in ViewDraw
- CMS Overview: Windows
- CMS Spreadsheets (Owners)
- Entering Constraints
- Buses
- CMS Netlist
- Assigning Classes
- Assigning Groups
- Board Stackups
- Export to Scratchpad
- Constraint Editor
- Constraint Sets and Display Groups
- Advanced Feature: "Actuals" Formulas
- Creating CMS Reports
Module 8 - Placement Prototyping with Planview
- ePlanner Methodology: Interconnect Planning (ViewDraw Flow)
- ePlanner Methodology: Interconnect Planning (Cadence/Mentor DA Flow)
- Planview
- Visibility Browser
- Netlist Browser
- Component Placement Commands
- Viewing Planview
- Scheduling Nets
- Scheduling PORT_CONTROL
- Constraining Segments
- Applying Schedules to Buses
- Simulating Nets
- Chaging Models in Planview
Module 9 - PCB Netlisting and Post-Layout Analysis
- ViewDraw/PCB Data Flow
- ViewDraw Netlisting for CAD
- Configuration Preferences
- CMS Constraints
- ViewPCB
- Mentor DA/Board Station Data Flow
- Mentor Board Station: Net Constraints
- Mentor Board Station: Component Placements
- Concept/PCB Data Flow
- Post-Layout Extraction
- Crosstalk Thresholds
- Post-Layout Analysis
- EyeWave
- BoardView
- XTK Sign-off: Post-route Verification
