I/O Designer
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| Date Begins | Date Ends | Time | Location | Register |
|---|---|---|---|---|
| Mar 01, 2012 | Mar 02, 2012 | 9:00am - 5:00pm | Longmont, CO | Register |
Duration: 2 Days
Pricing: $1,400.00 USD
Course Part Number: 221966
Contact us for details about training at your site
Course Overview
As the FPGA devices grew larger, it is harder to maintain consistency between the FPGA and PCB design flows. I/O Designer bridges the gap between the two design flows. This course offered by Mentor Graphics teaches you how to manage the data and monitor the changes between the two design flows while maintaining consistency. Both the lectures and hands-on labs provide you with skills necessary to use the tool efficiently in the design process, under the guidance of our industry expert instructors.
You will learn how to
- Use I/O Designer in different design scenarios
- Create an I/O Designer database
- Assign signals read in from a HDL file to the FPGA device pins
- Automatically unravel signals and buses based on the PCB floorplan
- Create symbols using different fracturing schemes
- Export the created symbols to a schematic tool
- Update and synchronize the changes between the two design flows
- Use I/O Designer to optimize Multi-FPGA Designs
- Manage the database in a team design using version control mechanisms
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using I/O Designer software. Hands-on lab topics include:
- I/O Designer GUI and software configuration
- Setup of FPGA/PCB projects in various design environments and design styles
- Defining the FPGA I/O design either in I/O Designer or the FPGA flow or the PCB flow
- Generation of the schematic sheets and symbols and the FPGA PCB mapping data
- Update and synchronize changes between the two design flows
- Use I/O Designer to optimize Multi-FPGA Designs
- Manage the database in a team design using version control mechanisms
Prerequisites
- A general understanding of PCB and FPGA design flows
- Knowledge of schematic capture and PCB layout