Design-for-Test: Scan and ATPG
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Duration: 4 Days
Pricing: 2,000 GBP (2,960 EUR)
Course Part Number: 057857
Description
The Design-for-Test: Scan and ATPG course is designed to drive the development of your skills and knowledge in scan and ATPG design processes utilizing Mentor Graphics tools: DFTAdvisor, FastScan, , MacroTest, DFTInsight and ModelSim®.
This course teaches you how to insert full scan in a design using the DFTAdvisor tool flow, and shows you how to create high quality test patterns using the FastScan tool flow.
The hands-on labs are designed to reinforce key concepts through practical experience and to develop proficiency with Mentor Graphics DFT tool suite under the guidance of our industry-expert instructors.
You will learn how to
- Configure scan chains/test logic and insert full scan
- Understand ATPG messaging
- Achieve high test coverage
- Create high quality patterns
- Understand advanced test methodologies
- Troubleshoot areas of low test coverage
- Troubleshoot DRC and simulation mismatch
Hands-On Labs
- Using the Graphical User Interface (GUI)
- Accessing information
- Scan and ATPG tool flow (with and without a design rule violation)
- Setting up new and existing scan pins (internal or external)
- Balancing scan chains with multiple clock domains
- Writing and editing scan chain order files and stitching
- Reading and analyzing messages
- Determining the cause of undetected faults and adding Nofaults
- Common methodologies to attain a quick estimate of test coverage
- Creating and saving patterns in different formats
- Verifying patterns using ModelSim®
- Reading ASCII files into FastScan
- Modifying timeplates
- Compression techniques
- Creating fault models and fault grading
- MacroTest and top-up ATPG
- Fault grading boundary scan and top-up ATPG
- Troubleshooting areas of low test coverage
- Troubleshooting DRC and simulation mismatch-full tool flow
- Debugging mismatches with automated tool
Audience
- Designers, Design-for-Test Engineers and Test Consultants involved with creating testable ASICs and ICs and producing the manufacturing test sets
- Traditional test engineers
- CAD engineers and managers
- CAD staff seeking to understand the effect of DFT on the design flow
Prerequisites
- Experience with UNIX environments
- A basic background in DFT
Key Points
- Basic scan concepts and DFT flow
- Accessing SupportNet information
- Scan and ATPG flow
- DFTAdvisor tool flow
- Design Rules Checking (DRC)
- DFTInsight
- FastScan tool flow
- Full scan
- Inserting test logic
- Defining pins
- Balancing scan chains
- Clocks
- Test coverage reporting
- FastScan pattern types
- Reuse, debugging, and diagnostics
- Time-based verification
- Creating and optimizing patterns
- Black boxes
- Testing embedded memories
- Boundary scan
- Top up ATPG
- Fault grading
- Troubleshooting areas of low test coverage
- Hierarchy browser
- Fault classes
- Debugging bus contention
- Analyzing DRC violations
- Handling C1, C3, C6, D5,D6, E4, E10, T3 , T4, T5, and various other DRC violations
- Debugging simulation mismatches
- Clock skew problems
- Timing violations
- Chain test