ModelSim Advanced Topics

Duration: 2 Days
Pricing: 900 GBP (1,300 EUR)
Course Part Number: 210193

Description

ModelSim® Advanced Topics teaches you to capitalize on the extensive capabilities of ModelSim to effectively and efficiently analyze and debug digital HDL designs. Using various ModelSim features and techniques, you will learn how to produce higher performance models and higher performance and more reliable resultant designs. Hands-on lab exercises reinforce lecture and discussion topics and provide you with tool usage experience under the guidance of our industry expert instructors. You will be presented with real world design challenges and the tools and support to develop high quality test benches to stimulate and analyze designs under test and resolve these challenges in a methodical manner.

You will learn how to

• Use advanced debugging concepts and methods
• Address advanced design topics and issues
• Take advantage of advanced cross-window capabilities supporting debugging
• Create and compare multiple datasets
• Use "Virtual Objects" to explore designs under test
• Manipulate designs and the ModelSim® environment using Tcl/Tk
• Debug multiple types of specific design errors
• Determine design "Code Coverage" for verification scenarios
• Perform advanced design probing with "Signal Spy"
• Use advanced waveform comparison features
• Customize design monitors and comparators using Tcl/Tk
• Use the Memory and Statistical profiler to find bottlenecks in your oe
• Use ModelSim for simulating Verilog 2001, SystemVerilog, SystemC and VHDL 2002 designs
• Create Value Change Dump (VDC) files
• Analyze and improve design and end product performance from high level abstract design description through gate level implementations

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using ModelSim® under the guidance of our industry expert instructors. Hands-on lab topics include:

• Using Tcl/Tk to customize ModelSim
• Debugging logic errors
• Debugging internal bus problems
• Debugging design stability challenges
• Backtracking Unknown signal states
• Debugging Foreign Language Interface problems
• Determining Code Coverage and resultant reliability
• Design probing using signal spy
• Waveform comparison
• Performance analysis
• Debugging Programming Language Interfaces problems
• Creating a design using SystemVerilog and DPI, and Verilog and PLI
• Creating Value Change Dump (VCD) files

Audience

Hardware, Software and System Engineers who perform VHDL, Verilog, SystemVerilog, SystemC or mixed-VHDL/Verilog simulation and analysis.
 

Prerequisites

• The student should have VHDL or Verilog knowledge prior to attending this course
• The student should have beginner ModelSim® skills prior to attending this course  or take the ModelSim HDL Simulation class.

Key Topics

• Design debugging
• ModelSim® customization with Tcl/Tk
• Viewing multiple datasets
• Waveform comparison
• Code Coverage analysis
• Performance analysis