Keynote Speakers

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Keynote Speakers

Special U2U 2008 Speaker

Steven Wozniak
Co-founder of Apple, Inc.

Silicon Valley icon and philanthropist for the past three decades, Steve Wozniak helped shape the computing industry with his design of Apple’s first line of products, the Apple I and II, and influenced the popular Macintosh. For his achievements at Apple Computer, he was awarded the National Medal of Technology by the President of the United States in 1985, the highest honor bestowed on America’s leading innovators

In 2000, Mr. Wozniak was inducted into the Inventors Hall of Fame and was awarded the prestigious Heinz Award for Technology, The Economy and Employment for “single-handedly designing the first personal computer and for then redirecting his lifelong passion for mathematics and electronics toward lighting the fires of excitement for education in grade school students and their teachers.”

Making significant investments of both his time and resources in education, Steve Wozniak “adopted” the Los Gatos School District, Los Gatos, CA providing students and teachers with hands-on teaching and donations of state-of-the-art technology equipment

Mr. Wozniak founded the Electronic Frontier Foundation, and was the founding sponsor of the Tech Museum, Silicon Valley Ballet, and Children’s Discovery Museum of San Jose, CA.

Steve Wozniak is also a published author with the release of his autobiography, iWoz: From Computer Geek to Cult Icon, in September 2006 by Norton Publishing

Optimizing Cross-Discipline Design

Chad Hawkinson
Vice President, Vertical Market Strategy
PTC

Today's high tech products represent a tight coupling of increasingly complex mechanical form factors, sophisticated electronics and more and more software-enabled features. Companies designing these products struggle to coordinate the different design disciplines in a way that leads to high quality products delivered on time. PTC and Mentor Graphics have partnered to solve many of the key challenges between different mechanical and electrical design teams, as well as to tie the hardware teams closer to the software development teams. This session will introduce these exciting product concepts to help you take your electromechanical design process to the next level.

Biography:

In his current position, Mr. Hawkinson is responsible for product strategy and solutions marketing for PTC products aimed at the high technology industry. Prior to PTC, Mr. Hawkinson held a variety of roles in high tech electronics manufacturing and supply chain software application development, including several years as a product manager for mobile Pentium processors at Intel.

Meeting the Critical Challenges of IC Implementation

Joe Sawicki
Vice President and General Manager, Design-to-Silicon Division
Mentor Graphics

In 2007 Mentor Graphics acquired Sierra Design Automation, allowing Mentor for the first time to provide a complete IC Implementation Flow from physical design, through verification, mask enhancement, production testing and failure diagnosis. Sierra brought breakthrough technology to Mentor in the form of the Olympus-SoC place and route system—technology like DFM-aware routing and Multi-Corner Multi-Mode optimization that is critical to IC implementation at 45nm and beyond. Combining Olympus-SoC with the industry-leading Calibre physical verification and design-for-manufacturing platform, and Mentor Design-for-Test and Yield Analysis platform, provides the most comprehensive IC implementation environment available today. By merging the development of these three industry-leading platforms into a single Design-to-Silicon division, Mentor has begun to drive platform integration based on a common vision for delivering first-pass silicon success.

This presentation will outline the critical challenges facing Mentor’s customers implementing industry-leading “system-on-chip” (SOC) integrated circuits at sub-45nm process nodes. Mr. Sawicki will describe the key technologies that Mentor is delivering to ensure its customers’ success at advanced nodes, including both advances in specific design, verification and testing tools, as well as cross-platform integrations to deliver new capabilities based on data sharing across the entire implementation flow

Biography:

Joseph Sawicki is the Vice President and General Manager of the Design-to-Silicon division. A leading expert in IC nanometer design and manufacturing challenges, Sawicki is responsible for Mentor's industry-leading design-to-silicon products, including the Olympus-SoC place-and-route system, the Calibre physical verification and DFM platform, and Mentor's design-for-test product line. Sawicki joined Mentor Graphics in 1990 and has held previous positions in applications engineering, sales, marketing and management. He holds a BSEE from the University of Rochester and an MBA from Northeastern University's High Technology Program.

Business/Management Track

A global increase in environmental regulation compliance is affecting the development of technology products like never before. Every stage of the product life cycle is impacted, including design, manufacture, upgrades, and material recovery. This year's Business/Management track explores some of the most important aspects of this topic, with senior management speakers from companies that are leading the way in how to most efficiently and responsibly meet these requirements

Getting Ahead of the Juggernaut: A Strategic Approach to Complying with Environmental Regulation

Michael Kirschner
President
Design Chain Associates, LLC

RoHS, WEEE, EuP, REACH, EWRA...these are acronyms for what is a sea change in the regulatory environment impacting the entire lifecycle of electronic products. The electronics industry approaches each of these individually and with silo mentality; while companies tend to view them tactically and often simply redirect existing personnel to address them. This approach has cost the industry a substantial amount of time, effort, and money, but are we actually improving anything? And are we (and regulators and consumers) getting our money's worth? In this talk we will discuss

• The context for these regulations - what are the drivers and why now
• How and where they impact the design, manufacture, and end-of-life of electronics
• The cost of compliance
• The common threads of product-targeted environmental regulation
• How the electronics industry and its supply chain can improve its efficiency in addressing these requirements
• Approaches for individual corporate strategy on improving product environmental performance

Biography:

Mike Kirschner has over 27 years of extensive cross-functional experience in all phases of the product lifecycle, from conception through production and end-of-life at both electronics OEMs and semiconductor suppliers. He has been President and Managing Partner of Design Chain Associates, LLC, which provides consulting services to the electronics industry on product-related environmental performance, since its inception in 2001 and is an internationally recognized expert in the analysis and impact of environmental regulation on electronic and manufactured products, as well as a sought after speaker and author. He has recently published two chapters in the "Governance, Risk, and Compliance Handbook", published by Wiley in 2008 and is featured in the new book "Exposed: The Toxic Chemistry of Everyday Products and What's at Stake for American Power," by Mark Schapiro. Prior to founding DCA Mike held Engineering and Engineering Management positions at Compaq, Tandem, Intel, and Intergraph, as well as at several start-ups in Component Engineering, Reliability, Quality Assurance, Software Development, and Product Design roles. Mike received his BSEE from Worcester Polytechnic Institute in Worcester, MA. Mike is a member of IPC's 2-18 committee on supply chain material declaration, The US TAG for IEC TC 108 on product safety, ASTM's F40 committee on declarable substances in materials, and is participating in the US EPA's ongoing development of the Electronic Product Environmental Assessment Tool, or EPEAT.

Nikhil Jayaram
Director of the Edge Router Silicon Group
Cisco Systems

In defining a forest, the language of tree species is used to articulate its biodiversity. Similarly, a need exists in the Information and Communication Technology (ICT) industry to define its “Green diversity”. However, ICT lacks a uniform taxonomy or language to do so. This presentation will focus on two issues, articulating Cisco’s “Green” roadmap and provide a proposed cross-functional “Green” language.

Cisco is driving environmental initiatives in three areas: responsible operations, product stewardship, and network architecture solutions.

Cisco is helping to reduce carbon emissions by making our operations and products more earth-friendly. In addition, Cisco believes that Information and Communications Technology (ICT) can play a central role by its “leverage effect” in reducing greenhouse gas emissions that contribute in large part to global warming.

Cisco’s vision is to use the Internet to monitor, manage and reduce electrical use in offices and homes. In cities, carbon emissions of idling vehicles in traffic can be significantly reduced through the use of smart communication technologies. High connectivity is poised to be the key to cutting carbon emissions.

Biography:

Nikhil Jayaram is responsible for the development of ASICs and network processors used in Cisco's mid-range and high-end routing products. The recently announced QuantumFlow Processor (QFP) was designed by his team and is currently shipping in the new ASR1000 router product family.

Nikhil has an MS in Electrical Engineering and 19 years industry experience. Prior to Cisco, Nikhil worked at Procket Networks, where he participated in the development of a Terabit class core router. Nikhil has worked on processors, I/O, compression, and graphics hardware in earlier stages of his career.

Best Practices in Reducing Hazardous Materials in the Design and Manufacture of Integrated Circuits

Stephen L. Tisdale
Packaging Manager, Customer Strategic Technology Integration Group

Environmental topics and issues are at the forefront for consumers, industry, activist groups, governmental agencies and society in general.  This trend presents both challenges and opportunities for the electronic designers and manufacturers.  Intel will share its view of the existing regulatory environment and what it is doing in terms of new technology development such as lead-free, halogen-free and energy efficiency technologies and present Best Practices that other companies can consider as they face these same challenges.

Biography:

Stephen Tisdale has been with Intel for four years and is a Packaging Manager in the Customer Strategic Technology Integration Group within the Assembly, Test & Technology Development Division. He received a bachelor’s in chemistry from Holy Cross College, an MBA in Operations from University of Massachusetts and a master’s in program management from George Washington University. Since joining Intel, he has worked on a number of lead-free and halogen-free projects, and chairs the Lead-Halogen-Free Steering Committee, which directs the integration of lead-free and halogen-free technology in Intel products. He is also involved in various consortia projects and addressing technical communications regarding pending legislation (RoHS II etc). Prior to joining Intel, Stephen held various engineering and R&D management positions within the electronics industry, and has more than 30 patents covering new material formulations, manufacturing processing and product design.

Environmental Requirements - Trigger for a New Library/IP Business Model?

Dr. Christopher Heer
Director, Library Development, Infineon

Increasingly tighter constraints due to environmental requirements force semiconductor companies to go for holistic approaches. While energy dissipation has been of particular focus in separate domains of the value chain in the past, new approaches trade-off measures from technology to system. Also, total system/product reliability is another criteria which requires much closer interaction between all levels. Therefore the provision of standard "one-fits-all" solutions will no longer be appropriate. Even more, future systems will exploit product specific IP components together with tailored standard IP and libraries.

The standard library/IP business has almost stagnated over the last several years, which drove quite a bit of consolidation. At the same time, many large independent device manufacturers (IDMs) abandoned their fab business, but kept IP and standard library know-how to retain the optimization levers along the value chain. Many large fabless seminconductor companies established or even re-built internal IP and library teams.

This presentation will explain the above mentioned technical triggers, but also the economic and strategic forces driving for these changes. Finally, an outlook for future technology nodes like 45nm and below will prove that this trend will even increase.

Biography:

From 1995 to 1999, Dr. Heer was with Corporate Research of Siemens in the 'VLSI System Integration' laboratory. Project scientist for MPEG video codecs and CMOS pixel sensors. Until 2003, he was head of the "Advanced Macros & Architectures" team at Infineon Technologies working on customized architectures for low power and high performance circuits for chipcards, communication and automotive. Currently, he is head of the global development organization for standard cell libraries, embedded memories and interface solutions at Infineon.

Special interests include VLSI architectures for high data rates, asynchronous circuits and the interface between process technology and circuit design.

Dr. Heer received his degree in Electrical Engineering from Aachen University of Technology (RWTH) in 1990, and his doctorate from the University of Ulm in 1995.

Green Electronics: Impact of environmental requirements on product design

Judy Glazer
Director, Global Social and Environmental Responsibility (SER) Operations
Hewlett Packard

Across the electronics industry, business leaders and IT professionals have made significant investments in the last few years to address the requirements of major environmental regulations such as RoHS, WEEE and now REACH. The industry now has new opportunities and challenges as customers seek to understand and control their own carbon footprint and the environmental impacts across the entire product lifecycle of the products that they purchase. For designers, these regulatory and market requirements can have major impacts on access to markets, cost, compliance, and customer satisfaction. They must be attacked cross-functionally because they impact design, procurement, manufacturing, sales, order management and support and the IT systems used to manage these processes.

HP’s strategy builds on a long history of reuse and recycling programs and materials innovation. This presentation will describe HP’s experience as a global manufacturer in meeting the challenges of new regulations and market requirements – including implications for both traditional design focus areas such as electrical performance and newly relevant design parameters. It will also discuss the long-term product design implications of the increasing regulation and scrutiny of the environmental impacts of electronic products.

Biography:

Judy Glazer is responsible for driving programs to implement SER policy into HP’s products and supply chain, from design and materials through manufacturing, distribution and end-of-life. This charter includes HP’s programs to measure and reduce the carbon footprint of HP’s ~$50B supply chain and implementation of HP’s supply chain code of conduct, as well as responsibility for leading HP’s environmental compliance programs.

Judy joined Hewlett-Packard in 1989 and has held a variety of supply chain and engineering roles. She holds MS and PhD degrees in Materials Science and Engineering from the University of California, Berkeley.