We recommend that all Board Station® and Expedition® users attend the “Optimizing Electromechanical Co-Design“ presentation during this open session. The Optimizing session, presented by Pawel Chadzynski from PTC, is in Grand Ballroom C.

Steve Shively | Board Station XE Sr. Product Manager | Mentor Graphics
Board Station XE has made tremendous strides in terms of capabilities and customer activity and usage. This presentation will provide users with a review of the major accomplishments this year with Board Station XE deliveries, and a peek at what is coming in the technology pipeline.

John Lee | Technical Marketing Engineer | Mentor Graphics
Board Station XE (BSXE) is the next generation design flow for Board Station customers and contains many new exciting capabilities to improve their design cycle times, designer productivity, and enable use of new PCB technologies. This 4-hour, hands-on workshop leads users through the new flow. The workshop will introduce attendees to the basic concepts of the BSXE flow including importing designs, usage of key layout capabilities, usage of the new Constraint Editor System™ (CES), generation of manufacturing outputs, and creation of drawings.

Pawel Chadzynski | VP, Product Management | PTC
Design of today's complex electromechanical devices requires ever closer collaboration between the electrical and mechanical domains. However, existing cumbersome tool-to-tool integrations and disconnected data management solutions across MCAD and ECAD design tools inhibit collaboration. As a result, collaboration between these domains doesn’t happen enough, resulting in errors, rework, and delayed time to market. This session explains how a new and emerging MCAD-ECAD collaboration technology can transform ECAD-MCAD design exchange to a process that enables a dynamic collaboration and management of incremental design changes. Emphasis will also be made on best practice approaches to connect Product Lifecycle Management (PLM) solutions with Mentor Graphic's DMS™ solutions to optimize process management across MCAD-ECAD co-design.

John Wilson | Consulting Engineering Manager | Mentor Graphics
Shorten design cycles. Increase functionality and performance. Constrain weight and cost. For engineers working on the electronic systems these are the major implications of trying to put more components into ever shrinking spaces while adhering to environmental constraints. Cooling these smaller spaces that often have higher electrical currents is even more challenging. Using the correct tools, such as CFD software, can help. In this example a PCB located in a automobile dashboard will be cooled by making use of copper traces and vias located in the board and the results will be compared to IR measurements. Additional applications for Computational Fluid Dynamics software will also be covered. These applications will include valve conception, car flow, catalytic converters and windshield wiper design. This presentation will feature products from Flomerics – now the Mechanical Analysis Division of Mentor Graphics.

Bob Laman | ECAD Manager | Waters Corporation
Over the last year, Waters Corporation has been transitioning their Design Environment from a Design Architect®, LMS, Board Station flow to the DxDesigner®, DMS, Expedition flow. This session will look at some of the business factors that drove our decision to adopt the new flow along with a discussion of migration issues that we have encountered. We will also look at how documenting best practices has helped to streamline our process.

Matt Wuensch | Business Development Manager | Mentor Graphics
Improving how Design and Manufacturing teams communicate with each other has been a constant topic of conversation, yet little substantive action has actually occurred until now. This session will look at truly effective strategies on how to not only improve the ability for these two different teams to communicate, it will show how these improvements can be easily implemented and that there is a direct benefit on product launch cycle times.

Ken Nishida | Application Engineer | Northrop Grumman
This presentation will discuss the DMS deployment at Northrop Grumman, Space Park with a focus on ECAD data in the enterprise, using DMS as the conduit to exchange data between the enterprise and PCB design tools, realizing concurrent design or development with ECAD, MCAD and other users of ECAD data.

Michael Kirschner | President | Design Chain Associates, LLC
RoHS, WEEE, EuP, REACH, EWRA...these are acronyms for what is a sea change in the regulatory environment impacting the entire lifecycle of electronic products. The electronics industry approaches each of these individually and with silo mentality; while companies tend to view them tactically and often simply redirect existing personnel to address them. This approach has cost the industry a substantial amount of time, effort, and money, but are we actually improving anything? And are we (and regulators and consumers) getting our money's worth? In this talk we will discuss

* The context for these regulations - what are the drivers and why now
* How and where they impact the design, manufacture, and end-of-life of electronics
* The cost of compliance
* The common threads of product-targeted environmental regulation
* How the electronics industry and its supply chain can improve its efficiency in addressing these requirements
* Approaches for individual corporate strategy on improving product environmental performance

Nikhil Jayaram | Director of the Edge Router Silicon Group | Cisco Systems
In defining a forest, the language of tree species is used to articulate its biodiversity. Similarly, a need exists in the Information and Communication Technology (ICT) industry to define its “Green diversity”. However, ICT lacks a uniform taxonomy or language to do so. This presentation will focus on two issues, articulating Cisco’s “Green” roadmap and provide a proposed cross-functional “Green” language.


Cisco is driving environmental initiatives in three areas: responsible operations, product stewardship, and network architecture solutions.


Cisco is helping to reduce carbon emissions by making our operations and products more earth-friendly. In addition, Cisco believes that Information and Communications Technology (ICT) can play a central role by its “leverage effect” in reducing greenhouse gas emissions that contribute in large part to global warming.


Specifically related to product stewardship, this includes design considerations on energy consumption, material selection, packaging, upgrading, and recycling. A major push is in the data center (server farms) architecture to reduce energy consumption. Also Cisco is working to maximize the life cycle of their products thru modular design and forward/backward compatibility as well as designing trade-in and upgrade programs. Cisco also promotes energy efficiency, reduced waste, and environmental improvements thru the Supply Chain.


Cisco’s vision is to use the Internet to monitor, manage and reduce electrical use in offices and homes. In cities, carbon emissions of idling vehicles in traffic can be significantly reduced through the use of smart communication technologies. High connectivity is poised to be the key to cutting carbon emissions. This presentation will offer examples of work Cisco is doing in this area.

Judy Glazer | Director, Global Social and Environmental Responsibility Operations | Hewlett Packard
Across the electronics industry, business leaders and IT professionals have made significant investments in the last few years to address the requirements of major environmental regulations such as RoHS, WEEE and now REACH. The industry now has new opportunities and challenges as customers seek to understand and control their own carbon footprint and the environmental impacts across the entire product lifecycle of the products that they purchase. For designers, these regulatory and market requirements can have major impacts on access to markets, cost, compliance, and customer satisfaction. They must be attacked cross-functionally because they impact design, procurement, manufacturing, sales, order management and support and the IT systems used to manage these processes.


HP’s strategy builds on a long history of reuse and recycling programs and materials innovation. This presentation will describe HP’s experience as a global manufacturer in meeting the challenges of new regulations and market requirements – including implications for both traditional design focus areas such as electrical performance and newly relevant design parameters. It will also discuss the long-term product design implications of the increasing regulation and scrutiny of the environmental impacts of electronic products.

Steve Tisdale | Packaging Manager | Intel
Environmental topics and issues are at the forefront for consumers, industry, activist groups, governmental agencies and society in general. This trend presents both challenges and opportunities for the electronic designers and manufacturers. Intel will share its view of the existing regulatory environment and what it is doing in terms of new technology development such as lead-free, halogen-free and energy efficiency technologies and present Best Practices that other companies can consider as they face these same challenges.

Dr. Christopher Heer | Director, Library Development | Infineon

Increasingly tighter constraints due to environmental requirements force semiconductor companies to go for holistic approaches. While energy dissipation has been of particular focus in separate domains of the value chain in the past, new approaches trade-off measures from technology to system. Also, total system/product reliability is another criteria which requires much closer interaction between all levels. Therefore the provision of standard "one-fits-all" solutions will no longer be appropriate. Even more, future systems will exploit product specific IP components together with tailored standard IP and libraries.

The standard library/IP business has almost stagnated over the last several years, which drove quite a bit of consolidation. At the same time, many large independent device manufacturers (IDMs) abandoned their fab business, but kept IP and standard library know-how to retain the optimization levers along the value chain. Many large fabless seminconductor companies established or even re-built internal IP and library teams.

This presentation will explain the above mentioned technical triggers, but also the economic and strategic forces driving for these changes. Finally, an outlook for future technology nodes like 45nm and below will prove that this trend will even increase.

Jeff Wilson | Product Marketing Manager | Mentor Graphics
In this session, the Calibre division will present the latest product updates and 2008 roadmap for DFM.

K.R. Balaji | Staff Engineer | Qualcomm
Sharad Pawar | Staff Engineer | Qualcomm
This presentation provides an overview of our infrastructure enabled using Calibre®DesignRev™ for executing DFM, DFY enhancement tasks. DFM, DFY enhancement tasks comprises of via doubling, metal via enclosure and dummy fill insertion and are performed on a physical design database after full chip assembly and physical verification is complete. This session will cover the methodology behind the infrastructure which is a common Application Programming Interface (API) constructed using Calibre WorkBench Commands that all tasks can share. The API is comprised of a GUI interface which lets the user prepare the input data for a task and a backend interface which performs the task on the gds opened in DesignRev. A technique for incrementally executing these tasks during ECO stage is also presented.

Michael White | Senior Calibre Product Marketing Manager | Mentor Graphics
At 90 nm and below, the dramatic increase in the number and complexity of DRC rules is taking a toll on DRC cycle time: from first-pass through tape-out clean. Mentor Graphics has a solution—Calibre nmDRC. Please join us to learn more about the revolutionary 2008 roadmap.

Shesha Krishnapura | Design Engineer | Intel
Multi-core compute platforms are the current Industry standard, while the majority of the EDA applications are still single threaded. In this session, we will explain how Intel is adopting multi-core platforms to deliver high performance computing for Intel silicon design with the current EDA applications, while bringing the data center efficiencies. We will share Intel’s multi-core platform technical specification, and the end-to-end EDA design flow based performance scaling numbers. We will list Intel software tools that are available and being used by EDA vendors to optimize their applications for multi-core.

Arya Raychaudhuri | Senior Design Engineer | Fastrack Design

Andrew Bartczak | Principal Electrical Engineer | Boston Scientific

This session provides an overview of Calibre Off-the-Shelf Software (OTSS) validation required by the Food and Drug Administration (FDA) for implantable medical devices. It is based on a Mentor generated Calibre Quality Assurance (QA) document combined with internal Calibre DRC/LVS in-house testing performed at Boston Scientific. The following Calibre QA issues will be emphasized first: product lifecycle models, release risk management and monitoring, defect classification, tracking and reporting, functional validation and regression testing, and quality metrics. Following the Calibre QA introduction, the session will cover these specific topics: project setup, performing Calibre DRC, LVS and XOR tests, regression suite and final results verification scripting, and correlation of vendor assessment of quality versus internal testing outcomes to complete OTSS Calibre validation.

John Dorsey | Principal Layout Engineer | ON Semiconductor
Jeff Bryan | Layoug Manater | ON Semiconductor
This session describes Methodologies developed by ON Semiconductor’s layout team to take advantage of the IC Assemble floor-planning tool using a top down design flow. This session will discuss real time use of the IC Assemble tool in a mixed signal, BCD design environment. Further discussions include the intricacies experienced debugging the tool and how we managed to apply the new tools to our technologies. In addition to learning a new floor planning tool, new methodologies were developed to support its use. This presentation will also discuss the ongoing methodology development for using the IC Assemble tool, and how we have mated many years of layout experience and proven technologies to a new design flow and floor planning tool.

Ronnie Hunt | CAD Supervisor | Advanced Bionics
This session will describe how our team has migrated two different environments of Mentor Database Management. I will talk about our experiences of phasing into the new Design Manager™ that will replace ICstudio™ and the old dmgr_ic. Pros and Cons and possible enhancements will be discussed as well as how this environment works with an ADMS design. The presentation includes answers to the question How easy is it to use?

Robert Yu | Staff Engineer | Cswitch Corporation
This session will describe how we use Perforce SCM as a high-performance, low-cost, and secure solution to manage all the data that goes into building our chips—including layout, schematics, source rtl, flows, software tools, verification, board designs, tech files and across multiple platforms at multiple sites.

Paul Tuinenga | Principle Staff Engineer | ISDE/Vanderbilt University
Building custom device models in the Generalized User Definable Models (GUDM or UDM) for Eldo® is not difficult. We present a working example of a nonlinear magnetics model (a two-terminal device) masquerading as a custom diode model, and answer many of these questions. Implementation is with the Microsoft Windows version of Eldo, which means the freeware version of Microsoft Visual Studio for C/C++ can be used for development. Topics covered include: device initialization, creating internal nodes and branches, calculating what the simulator expects, saving state information, tricks for determining initial time-steps, and debugging iteration-by-iteration or the breaking-pointing just before failure.

Tom Daspit | Product Marketing Manager | Mentor Graphics In this session, the CICD division will present the latest product updates and 2008 roadmap for the Custom-IC Flow, including Design Manager, DA-IC, IC Station, ICassemble, and other supporting products.

Michelle Lange | DO-254 Program Manager | Mentor Graphics
DO-254 is a recent standard that affects FPGA, ASIC and in some cases, even PCB design. Come to this session to see how DO-254 fits into the bigger picture of aircraft certification, what it entails, and what a typical compliance process looks like. Because DO-254 projects tend to be more costly and challenging than projects that do not have to comply with the standard, we discuss the design flow requirements of DO-254, the typical challenges, and how Mentor solutions can help you automate some of the more painful aspects of these flows. If you are manager or designer of airborne electronic hardware, and want to find ways to optimize both your design methodology and compliance requirements, you can't afford to miss this session. Leave with not only a better understanding of DO-254, but also tips on how to avoid common pitfalls that can negatively affect your project and your business.

Anders Nordstrom | FPGA Design Engineer | Ericsson
Krishna Prada Kalluri | System Manager | Ericsson
This session proposes a way to offload CPU for SIP message parsing. Today, most of the control plane traffic sent over IP infrastructure is text based and an http look-a-like. Parsing of these packets in software adds a significant load on CPU and also reduces throughput in the signaling path. Research at Ericsson found that “SIP message parsing can be accelerated with FPGA”. The presentation will focus on the outcome rather than tools.

Clifford Cummings | President | Sunburst Design
The introduction of SystemVerilog Assertions (SVA) added the ability to perform immediate and concurrent assertions for both design and verification, but some engineers have complained about SVA verbosity or do not understand some of the better methodologies to take full advantage of SVA. This session documents valuable SystemVerilog Assertions tricks, including: use of long SVA labels, use of the immediate assert command, concise SVA coding styles, use of SVA bind files, and recommended methodologies and best practices for using SVA.

Srikanth Muroor | Principal Engineer | Telegent Systems

Valerie Rachko | Marketing Director | Mentor Graphics
The past year has been very productive for Mentor’s HDL products as we’ve added 3 new tools and continued the enhancements of 4 others. This session will provide roadmaps and summaries of the significant advancements that were made to HDL Designer, Visual Elite HDL, Precision Synthesis and LeonardoSpectrum. Overviews of the new innovative products will be shared for managing requirements in your design and verification flows, for reducing OVM testbench creation time, and for advanced FPGA synthesis and timing such as physically-aware synthesis. These new and expanding areas of HDL design continue to strengthen Mentor as a lead provider of HDL products for ASIC and FPGA design and will add to your team’s productivity

Tim Harp | Senior Systems Engineer | Mentor Graphics
Jim Luick | Technical Lead | Mentor Graphics
The Mentor Graphics Installer is quickly becoming the prevailing vehicle for installing Mentor Graphics’ products. Calibre, ModelSim®, Expedition, Board Station and others are now using this technology to deliver software. While the Mentor Graphics Installer provides a simple out-of-the-box experience for an individual install, how can a System Administrator automate the installation to 10 or even 100+ workstations? This session provides an in-depth look at the new Batch Tool, and how an administrator can script the installation process into a robust, repeatable, unattended solution that will minimize the installation effort. This presentation covers how to set up a source repository for the installation media, creation of a “batch” script using the new Batch Tool and introduces various methodologies for executing the batch script. This session assumes the user is a System Administrator who is responsible for installing new software and patches onto many similarly configured machines.

Craig Butts | Senior Systems Engineer | VMware
This session provides an overview of VMware virtualization solutions. It includes a basic understanding of virtualization or hypervisor technologies, in addition to the other management and automation solutions offered by VMware. The presentation will include a discussion of the implications of OS licensing for virtual machines, and an overview of the newer features and enhancements.

Ken Foster | Senior Corporate Applications Engineer | Mentor Graphics
Among the many changes for Board Station XE 2007 on the Microsoft Windows platform is the introduction of two new UNIX emulation environments: The MKS Utilities environment and the Mentor Windows Environment. In this session, we'll discuss an overview of each environment and how to manage both environments on the same system.

Lauren Price | Marketing Manager | Acresso
Are you responsible for ensuring engineers can access Mentor licenses? Are you able to accurately plan and effectively negotiate software purchases? Can you easily demonstrate compliance with your vendor contracts? In this session, Carla Enfield from Lockheed Martin and Marjorie McGonigal from Acresso Software will share how the latest improvements to FLEXnet Manager, a Web-based license management solution, have helped Lockheed Martin achieve these goals and optimize their software investment. Marjorie will also discuss how Acresso’s launch as a new stand-alone software company benefits Mentor users, and she will offer a glimpse into the future direction of FLEXnet Manager that will help you and your organization become more efficient and productive.

Guy Wettstein | Senior Corporate Applications Engineer | Mentor Graphics
Please come and meet Mentor Graphics Environment CAEs, Licensing/Install/Platform representatives and engineers. There will be a brief introductory presentation followed by an informal Q&A session with a panel of licensing, install and platform experts.

Jackie Cooper | DFT Principal Engineer | Intel
As modular, re-usable SoC designs become more ubiquitous and design schedules are increasingly compressed, there is a demand in some markets for TestKompress® EDT insertion that is modular, generic, and not dependent on backend scan stitching. This session explains how this was successfully implemented for one complex, large SoC with 680,000 scan cells and 70 internal clock domains. It will describe the planning stages that defined the TestKompress EDT RTL generic module, the added RTL code wrapper that provided for a smooth clock transition from EDT module to device scan chain, and how it took care of the “every scan chain must have at least one scan cell” requirement. This presentation will finally address the advantages and disadvantages of this methodology.

Alon Sa'ado | ASIC Design Engineer | VIA Telecom
Mike Jones | PC Board Designer, Senior Staff | Mentor Graphics
With small fabrication technologies, at-speed (Transition Delay Fault) testing is essential to maintain high test quality and detect timing related defects. The most efficient and effective way to generate at-speed test is by using ATPG with transition fault model. This session presents a complete flow of At-Speed pattern generation. It describes the planning stage, the digital circuits that are needed, PLL programming, a description of the Name Capture Procedures (NCPs), the use of timing constraints to provide masking of false paths and multicycle paths and the scripts to generate Transition Delay Fault (TDF) patterns. We also include a description of the flow of generating Stuck-At Fault patterns to top-off the TDF pattern set.

Kanwaldeep Sobti | Senior Design Engineer | AMD
Anuja Sehgal | Senior Design Engineer | nVidia
With the ever increasing complexity and size of multi-core microprocessor chips, the need for higher on-chip test bandwidth is also increasing. Scan compression has been extensively used to alleviate the problems of constrained test bandwidth for such chips. Enhanced TestKompress (TK) further improves the availability of on-chip test bandwidth without an increase in chip area or pattern volume. It allows for an unequal number of input and output scan channels to the decompressor and out of the compactor, i.e., the decompression ratio can be lower than the compaction ratio. This session describes the use of Enhanced TK in AMD's new CPU core. We show that Enhanced TK can be effectively and efficiently used in the same infrastructure as conventional TK and can result in higher availability of chip level channel bandwidth. The additional channel bandwidth can also be used for increased parallelism in scan test, thereby reducing overall test cost.

Colin Renfrew | DFT Methodologists | Freescale Semiconductor
Ashu Razdan | DFT Design Engineer | Freescale Semiconductor
At-speed testing of a SoC with several clock domains presents the problem of isolation and accurate faulting of the logic within each domain during ATPG. The absence of specific and programmable controls of these clock domains during test requires the creation of an alternative solution. This session describes the methodology that was established to address this challenge. Specifically, it will cover how false and multi-cycle path information from Static Timing Analysis (STA) was used for clock domain partitioning and logic separation, how an on-chip PLL was controlled to run at-speed testing on each clock domain, and how this methodology was applied through FastScan™ and TestKompress for at-speed ATPG on a high-speed, 90nm SoC platform. Results from simulation as well as silicon will be presented as proof of concept.

Mahmut Yilmaz | Design Engineer 2 | AMD
Thomas Olsen | ATPG Engineer | AMD
Timing-related defects are becoming increasingly important in nanometer technology designs. Small-delay defects (SDDs) caused by various environmental effects and process technology parameters can potentially cause timing failure in a design and must be carefully taken into consideration during delay test. Commercial timing-aware ATPG tools, such as Mentor Graphics’ FastScan, have been developed in recent years as a result of the growing industry concerns regarding SDDs. Furthermore, conflicting market drivers of design cycle time, product quality, selling price and functional density (more functionality per unit area of silicon) require that all aspects of design, manufacture and test are as efficient and cost effective as possible. This session presents a case study of timing-aware ATPG using the FastScan tool. We compare timing-aware FastScan to traditional transition-fault ATPG and n-detect transition-fault ATPG in CPU run-time and effectiveness of detecting SDDs.

Paul Shupe | Staff Engineer | Mentor Graphics
This presentation explores the use of XML to represent IC component datasheet parameter information for standard analog components. XML offers advantages of casting parameter data in a stable, machine sensible format, which can be easily used to build databases, graphical interfaces, and drive analysis programs. This session shows how to apply the two standards for representing this data: the Component Information Dictionary Standard (CIDS), and the Pinnacles Component Information Standard (PCIS). These standards are applied to representing datasheet parameters for analog parts in Mentor Graphics’ AccuParts™ library. Examples and lessons learned are included in the session.

Ronald Haynie | PCB Librarian | Optimum Design Associates

This session will detail the process of translating a Mentor Graphics DC library to a DX library with the intention to use the "device place" by DxDataBook™ functionality. It will cover using Mentors' DC2DX translator, modifying the translated symbol to ensure it works properly, extracting attribute values from the existing PDB to place in the DataBook, new pdb creation, and a part checking process. It will focus on the steps needed to create a "stand-alone" schematic symbol including how to create the different hetero symbol types.

Anthony John | Senior EDA Applications Engineer | Rockwell Collins
This session will tell how Rockwell Collins, with the help of Mentor Graphics, implemented DMS™ and tied it into our ePD/DxDesigner®/DxDataBook environment.

Gary Lameris | Technical Marketing Engineer | Mentor Graphics
This session is an overview of the new database structure and translation, new features and enhancements from the 2005 DxDesigner release.

Rob Davies | Product Marketing Manager | Mentor Graphics
The 2007 release of DxDesigner was a major development of the product with its underlying architecture providing the platform for a truly concurrent design environment. As DxDesigner continues to evolve as the engineering cockpit for concurrent design, we will be adding new technologies and capabilities into the flow. In this session, Mentor will present the direction and roadmap for the product over the next twelve months.

Jayson Harames | PCB Design Engineer | L-3 Communications
Happy Holden does an extremely good job of discussing the merits of, and when to use, HDI. However, implementing new technologies into an existing process and tradition can be difficult. We will explore a 400 pin/inch design using Expedition with an advanced interconnect license. Many features within Expedition aided in the layout process that will be discussed including: multiple via objects, post route analysis and automation as well as some auto-route schemes that worked well with the advanced interconnect license.

Shaun Olsen | L-3 Communications
A Multiple Via Object (MVO) is a predefined group of vias or a via pattern that can be used when the current carrying capacity of the trace is a concern in the PCB. The MVO is invoked automatically when the user routes traces of certain widths. For example: if the design required the routing of 2 amp traces with a 0.065 trace width, the user could set up the MVO rule so that anytime the user routed a signal that was 0.065 wide, the user would have 4 vias automatically available to place when the trace changed layers, connected to another trace or connected to an area fill or plane area.

Alex Diaz | PCB Board Designer | Broadcoom
John Mehlmauer | Engineer, Senior Staff PCB Layout | Broadcom
Our PCB designers were given a requirement to accomplish length matching within a differential pair. This involves applying serpentining or sawtooth routing to a trace. Doing this routing manually is a tedious and time consuming task. By using automation, the time and effort needed decreases significantly. Expedition’s automation layer provides all the tools needed to solve this problem. This session will demonstrate how the script form editor and automation object model was used to create an interface for applying a sawtooth route on an existing trace to achieve proper length matching for differential pairs.

Nils Wittler | Senior Manager CAD/CAE Support | Fujitsu Siemens Computers
Changing the complete PCB design flow compares to starting a trip to an unknown territory. It sounds promising but you hesitate taking the first step out of your door, leaving your well known environment and moving out of your comfort zone.

But sometimes this step is necessary or even overdue, don't wait for your competitors being first and risk yourself to fall behind. Plan carefully, estimate the risks and the benefit, take your decision and be prepared to reconsider everything.

Fujitsu Siemens Computers has migrated from a mixed non-Mentor flow to Expedition Enterprise starting in 2003. This presentation is both, a look back on the migration project and sharing best practice to achieve excellence in a highly competitive business. It should be helpful for others in the community facing the same task. We will take you on a journey through our migration process to the place we are today and where we want to be tomorrow.

Mark Laing| SMS Product Marketing Manager | Mentor Graphics
With the changes in today’s Printed Circuit Board (PCB) technologies, it has become more challenging to optimize test and inspection strategies to balance the needs of quality, throughput and cost. A significant number of the today’s designs cannot achieve the required quality level based on traditional In-Circuit Test (ICT) alone. Reductions in bed of nails accessibility means that more and more emphasis must be placed on Design For Test (DFT) and the utilization of complementary process verification techniques. All PCB manufacturers create defects in their process but with intelligent implementation of Design For Test practices these defects can be caught and addressed in a timely manner

Thomas Leitner | Digital Design | DICE gmbH
This session discusses our efforts in realizing an efficient verification environment based on transaction level modeling. The pilot project is a digital phase locked loop, which consists of a digital part (control unit) and an analog part (control process). We took some actions to verify the control unit, including:
• Leveraging state-of-the-art verification methodologies supplied by a sophisticated hardware verification language (SystemVerilog)
• Improving simulation performance by raising analog models to transaction level
• Inducing imperfections inside the control process by using constrained randomization
These imperfections are to be compensated for by the control unit by utilizing the OVM framework for building an efficient testbench infrastructure with self-scoring capabilities. A future approach is to derive specific block parameters from analog Monte Carlo simulations. This approach will gain accuracy in the randomization of real-world corner cases.

Cliff Cummings | President | Sunburst Design
In several well-known SystemVerilog verification methodologies virtual interfaces have an important role, tying class-based verification components to other design and verification blocks. Various clarifications and additional features for virtual interfaces have been proposed for inclusion in the IEEE SystemVerilog P1800-2008 Standard. This session will discuss applications of virtual interfaces, give justification for the proposed changes, and consider the impact those changes will have on design and verification methodology.

Alex Kumets | Consulting Engineer | Qualcomm
The most painful part of modern ASIC design is verification relating to fast changing portions of design because of bugs, changing functionality or an ECO from marketing. A crucial question is what should we check and where new code may introduce problems. Unfortunately, the old design often does not have proper documentation test vectors and test bench. The proposed algorithm should highlight all possible points where the new code may create problems. The tool to achieve that is formal verification as a Language Equivalence Checker (LEC) and a simple Perl script. The LEC has to compare two RTL-based representations of the same design: the old one (before modification) and the latest one. A file which has 'logic cones' definitions as an output from LECi is used by a Perl script to parse the output file and insert an error into old design representation and rerun LEC.

Ning Guo | Principal Consulting Engineer | Paradigm-Works
Stephen D'Onofrio | Verification Architect | Paradigm-Works
OVM (Open Verification Methodology) is the result of joint development by Mentor Graphics and Cadence. It combines the Mentor Advanced Verification Methodology (AVM) and the Cadence incisive Plan-to-Closure Universal Reuse Methodology (URM).

As users of both AVM and URM methodologies, we have existing testbenches that were developed for each individual methodology. During the process of migrating from our existing AVM-only and URM-only testbench to OVM testbench, we were able to understand better on how the two methodologies complement each other in the OVM.

Using the same design under verification, we will describe the testbench facilities in each methodology and compare the similarities and differences between them. We will specifically discuss aspects of stimulus generation, response checking, scoreboarding, and testbench architecture in each of these methodologies. Finally, we will briefly describe our OVM testbench’s configuration control mechanism, virtual sequence, and factory capabilities.

Finally, we will talk about generating an OVM based testbench automatically using a template generator. The template generator allows users to generate a customized OVM-based environment, it enforces a consistent look and feel, and it enables rapid development and maintenance of the verification code across multiple-sites and cultural barriers.

John Gryba | Hardware Designer | Alcatel Lucent
This session provides an overview of the steps involved in creating a board level functional simulation environment using Seamless® and how that environment can be leveraged to do software/hardware co-verification. We begin by documenting the objectives of board level functional simulation and software/hardware co-verification. Then we outline the verification flow and a verification environment using Seamless. Different verification methods are discussed to address certain verification challenges. We conclude by describing the benefits derived, lessons learned, and some advice in getting started with Seamless.

Terry Fox | Signal Integrity Consultant | Terry Fox & Associates
Terry Fox has been active in signal integrity since the days of the Mentor/Daisy/Valid CAE wars of the 1980s. After trying for a while to sell SI tools to companies with SI problems, Terry realized a better solution was to be in the business of solving those SI problems. Terry will talk about numerous instances where he has needed to provide "disaster recovery" and how such instances can be avoided in high-speed designs.

Alex Golian | Principal Engineer | Northrop Grumman As signal rates increase, rise times decrease, routing densities increase, and high speed serial transmission line lengths increase, so do crosstalk problems and issues. The purpose of this paper is to present an intuitive approach to the understanding of crosstalk and how it relates to, among other things, signal rise time, transmission line structure, and stack-up design. It explains, near and far end cross talk, and the fundamental causes of each. It will be shown how to build simple models in Hyperlynx 7.7 to view and understand classic near and far end cross talk signatures, and how to build complex models for board level simulations to detect crosstalk among thousands of nets using Hyperlynx BoardSim. This presentation will also offer a better understanding of excitation states referred to as odd and even modes, and signals and impedances referred to as common and differential, toward a more fundamental and intuitive understanding of crosstalk. Finally, it will be shown how RF, microwave, and high speed digital designers are concerned with the same phenomenon, just from a different perspective.

Kim Owen | Application Engineer Consultant | Mentor Graphics
This session provides an example of how to use Mentor Graphics tools to implement a successful DDR2 design. The session will take you through the steps of creating signal quality and timing strategies, entering constraints to drive place and route, leading to a routed board. The routed board will then be analyzed to ensure it meets the DDR2 electrical Signal Integrity and routing requirements.

Weston Beal | Corporate Application Engineer | Mentor Graphics
It's well known that Mentor Graphics signal integrity tools can simulate nets with SPICE, VHDL-AMS, and S-parameter circuits, but sometimes getting those models into the simulator proves difficult. This session explains case studies of how to get SPICE and S-parameter models from different sources to work correctly in either HyperLynx®, ICX®, or ICXpro.

Please refer back for more details.

Yan Killy | Technical Marketing Engineer | Mentor Graphics
In this session, you will get hands-on training using PADS Router. You will learn both the basic and advanced features of the interactive router, including high-speed routing. Our instructor will share PADS Router "tips and tricks". Feel free to bring your own designs to work with, and have the instructors offer suggestions on how to address your specific routing challenges!

Yan Killy | Technical Marketing Engineer | Mentor Graphics
This session will review PADS' features such as Physical Design Reuse, DFT Audit, RF design features, and more. Get hands on experience with these features and learn how to better address your design challenges. Feel free to bring your own designs to work with, and have the instructors offer suggestions on how to address your specific design challenges!