Enterprise Variant Manager
Tuesday, November 4, 2008 | 8:00am - 12:00pm
Terry Lovell, Technical Marketing Engineer, Mentor Graphics

In this 4 hour workshop, participants will be introduced to the new Enterprise Variant Manager (EVM) environment.  Fundamentals of how-to define and set up Physical Variants and/or the recently implemented more powerful Function Managed Variants (FMV) within the DxDesigner®/Expedition™ PCB design flow will be reviewed and demonstrated.   In addition, participants may be required to step through this same process during the lab portion of the session using the EVM tools.  Participants will become familiar with the power and strengths that EVM provides and how to position strategies of implementation into their own specific corporate environments.

After this workshop, participants will be able to:

• Create Physical and Function Managed Variants within DxDesigner
• Set up and process manufacturing variant views within Expedition™ PCB, and create/display variant views within FabLink™ XE and the Drawing Editor.
• In addition, participants will learn how to generate other variant manufacturing outputs like Bill-of-Materials (BOM) and PDF drawing outputs.

Breaking New Ground in PCB RF Design
Tuesday, Novmeber 4, 2008 | 8:00am - 12:00pm
Loy D'Souza, Technical Marketing Engineer, Mentor Graphics

RF and wireless technology content is becoming mainstream in a variety of designs today and managing mixed technology designs is increasingly difficult and time consuming. Unlike the previous process of incompatible RF and PCB part libraries and ASCII translation of designs, this session focuses on a new integrated flow that delivers a new design paradigm with radically new RF functionality.

Critical RF Design topics in this workshop include:

• Full RF parametric shapes support
• Synchronization with Agilent libraries to access the latest RF models
• Specific clearances relative z-axis for RF circuits in order to more effectively create a faraday cage for RF circuit isolation
• RF mitered and curved traces for RF simulation complaint interconnects
• Easy-to-use stitching via algorithms for RF ground planes

Upon completion of the workshop, participants will understand that:

• RF circuits can now be designed as real circuits directly in PCB schematic or be transferred to PCB design from Agilent ADS
• There can be more than schematic “black boxes” but true RF schematic in the system-level design

Advanced Constraints Routing
Tuesday, November 4, 2008 | 8:00am - 12:00pm
Friday, November 7, 2008 | 8:00am - 12:00pm
Steve Herbstman, Technical Marketing Engineer, Mentor Graphics

AutoActive Smart Utilities
Friday, November 7, 2008 | 8:00am - 12:00pm
Tammie Warner, Corporate Application Engineer, Mentor Graphics

Smart Utilities is a series of automation utilities that have been added to the EE2007.1 and BSXE2007.2 release to provide additional routing capabilities, drawing and viewing functionality for Autoactive users. Smart Utilities addresses various Autoactive routing usability and Advance Technology Pro (Flex) circuit design improvements. The workshop will include demonstrations of the Smart Utility functions and a hands on lab.

Upon completion of this workshop, participants will be able to utilize the Smart routing utilities to expedite cumbersome routing routines within the Autoactive PCB environment.

Effective BGA Fanouts
Tuesday, November 4, 2008 | 8:00am - 12:00pm
Charles Pfiel, Director of Engineering, Mentor Graphics

Very large BGAs over 1500 pins present unique challenges for routing.  Generally, simply routing out of these devices is the greatest contributor to signal layer count.  Effective fanout patterns are the key to successful routing of large BGAs.  This workshop explores numerous fanout methods in the context of laminated and HDI stackups to increase route density and thereby reducing layers.  This workshop is based on the new book by Charles Pfeil titled, “BGA Breakouts and Routing”.

At the end of the workshop:

• New software that automatically generates fanouts in Expedition PCB and Board Station XE will be demonstrated

HyperLynx Advanced Simulation
Tuesday, November 4, 2008 | 8:00am - 12:00pm
Friday, November 7, 2008 | 8:00am-12:00pm
Patrick Carrier, Technical Marketing Engineer, Mentor Graphics

ESL Timing and Power Optimization at the System Level
Tuesday, November 4, 2008 | 8:00am - 12:00pm

System development faces significant challenges to understand the combined impact of the hardware and software architecture on system power, performance and functionality.  The most common approach today is to develop the hardware and software features in isolation, integrating and testing at the end of the design cycle.  As a result, schedules are delayed and the opportunity to make architectural modifications is lost.

Key questions need to be answered at the architectural level. Does it deliver the necessary functionality and meet user expectations?  Do I understand and can I quantify the performance goals for timing and power consumption?  Can I implement the system?

Mentor Graphics provides ESL tools and methodologies that can be deployed to integrate HW and SW early in the process, explore architectural trade-offs, ensuring that these questions are answered and the optimal system is built correctly the first time.

In this workshop, we will provide an approach to run SW on a virtual platform, architecting and analyzing the system for overall performance improvement and specifically address timing and power optimization.

Learn about:

• Mentor Graphics’ unique Scalable Modeling Methodology
• Advanced HW/SW debug techniques
• Mapping physical power into TLM
• Power and performance use cases and optimization methods

Labs include:

• Creating fast, accurate power and performance TLM models
• Graphical System Assembly
• HW/SW validation and analysis of the SOC platform
• Characterize accurate power attributes for fast simulation
• Creating a virtual prototype for distribution to the SW teams
• Utilizing pre-define generic models for upfront architecture power analysis

Tools include:

• Vista™ l Product Line, Visual

Getting Real with OVM
Tuesday, November 4, 2008 | 1:00pm - 5:00pm
Tom Fitzpatrick, Verification Technologist, Mentor Graphics

This workshop will present a full technical introduction to the Open Verification Methodology including usability and debug enhancements in Questa®. It then looks ahead to map out its future development direction. The scope and content is therefore suitable for both new users to the OVM and for those who have already had some exposure.

OVM is a true open source verification methodology standard and was developed by co-operation between Mentor Graphics and Cadence Design Systems

At the end of this workshop, participants will understand:

• The significant features of OVM, as detailed from a user's perspective, and its application will be illustrated in the context of Questa.

Design-for-Test
Tuesday, November 4, 2008 | 8:00am - 5:00pm
Troy Cox, Corporate Application Engineer, Mentor Graphics

Attend this full day workshop on Design-for-Test to learn hands-on techniques in the following areas:

• Experience Production Volume Yield Learning with labs
• Debugging Areas of Low Test Coverage  with labs
• In depth look at TestKompress® Xpress
• Debugging TestKompress K DRC Rules with labs
• Automated Simulation Mismatch Debug with demo

IC Flow
Tuesday, November 4, 2008 | 8:00am - 5:00pm
Chris Cone, Technical Marketing Engineer, Mentor Graphics

The layout of analog, mixed-signal, and custom digital ICs must be finely tuned to meet strict constraints on performance, area, power, manufacturability, and yield. To minimize schedule impact while achieving these goals, the designer can now capture and manage constraints. This design intent automatically drives the layout implementation. This new methodology can significantly accelerate layout productivity without compromising quality and flexibility, including across globally disperse teams.

In this workshop, we illustrate:

• How constraints can be captured, managed and implemented in Mentor's IC Flow platform

Automation and Customization in the Expedition Enterprise Flow
Tuesday, November 4, 2008 | 8:00am - 5:00pm
John Dube, Staff Engineer, Mentor Graphics

The Expedition Enterprise design flow has a very powerful customization capability built on top of standard-based automation technology. End-users can create scripts that enhance their productivity by automating repetitive design tasks, CAD support teams can develop scripts that improve the overall design team efficiency and quality, and system administrators can develop scripts to ensure smooth integration with the corporate environment.

This workshop will:

• Introduce the concepts and techniques that are used in typical flow customizations, with emphasis on the new functionality available in the EE2007.x releases
• In addition, customers will share their experience with automation, and demonstrate how they have effectively used automation in DxDesigner, CES, Expedition, and FabLink XE

Upon completion of the workshop:

• Participants will have an understanding of how to customize and extend the applications in the Expedition Enterprise design flow

DMS - Managing an Enterprise Flow
Tuesday, November 4, 2008 | 8:00am - 5:00pm
Andre Mosley, Technical Marketing Engineer, Mentor Graphics

This hands-on workshop will acquaint participants with the new features of DMS with a focus on the Expedition Enterprise flow. The following technologies will be discussed in detail:

• DMS Import Manager: Wizard to create a DMS datamodel and load component data
• DMS Connector with DxDatabook: Integration of DxDatabook with DMS (DataFusion)
• Enterprise Library Management: Customizing the Enterprise part request flow
• Variant BOM Management: Loading and versioning BOM data from DxDesigner
• Reuse Block Creation & Management: Managing and deploying IP with DMS
• Compliance Management: Defining compliance specifications (ROHS, WEEE, MFG, AVL, etc.) with automatic component/design auditing

Board Station XE
Tuesday, November 4, 2008 | 8:00am - 5:00pm
John Lee, Technical Marketing Engineer, Mentor Graphics

Board Station® XE (BSXE) is the next generation design flow for Board Station customers and contains many new exciting capabilities to improve their design cycle times, designer productivity, and enable use of new PCB technologies. This 4-hour, hands-on workshop leads users through the new flow. The workshop will introduce attendees to the basic concepts of the BSXE flow including importing designs, usage of key layout capabilities, usage of the new Constraint Editor System (CES), generation of manufacturing outputs, and creation of drawings. During this workshop, participants will learn:

• Recognize the file structure differences for a BSXE design
• Validate their libraries for use in the BSXE flow
• Import an existing Board Station Layout design into BSXE
• Generate plane data with the new Dynamic Planes Engine
• Control the results of the Dynamic Planes Engine
• Control forward- and back-annotation processes
• Enter and edit constraints in the new CES
• Generate common manufacturing outputs using FabLink XE Pro
• Create drawing documents for their designs using the Drawing Editor

Calibre® TVF
Tuesday, November 4, 2008 | 9:00am - 4:00pm
John Bierbauer, Learning Product Development, Mentor Graphics

This workshop will help participants unleash the powers of TVF to make SVRF files more compact, easier to maintain, and more powerful. Detailed lab exercises help reinforce the lectures and provide participants with extensive tool usage experience under the guidance of our industry expert instructors.

Attendees will learn how to:

• Incorporate TVF concepts into SVRF files to make rule writing easier
• Create Compile Time and Runtime TVF SVRF files
• Use Calibre TVF to make SVRF files easier to maintain

Hands-On Labs:
Throughout this workshop, extensive hands-on lab exercises provide practical experience using Calibre TVF software. Hands-on lab topics include:

• Review of Tcl concepts
• Basic use of Runtime and Compile Time TVF rule files
• Using Compile Time TVF to create DRC rulechecks
• Using Runtime TVF to create TVF Functions
• Combining Runtime and Compile Time TVF

Calibre nmDRC/nmLVS/PERC/xRC: New/Latest Functionality
Tuesday, November 4, 2008 | 9:00am - 4:00pm

Calibre is the industry standard for Deep Submicron Physical Verification.  This workshop will cover the latest features and new functionality of Calibre nmDRC and nmLVS. The lecture modules explain the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset, focusing on new 2008.X functionality including:

• LVS debug
• Incremental DRC
• Hyper scaling
• DRC waivers
• Using xRC at 45nm (in-die variation and making use of PEX ALIAS/IGNORE)
• Hyper scaling

This workshop will teach participants to:

• Effectively use the latest features and new functionality of Calibre nmDRC and nmLVS

Formal Design Reuse
Tuesday, November 4, 2008 | 1:00pm - 5:00pm
Terry Lovell, Technical Marketing Engineer, Mentor Graphics

In this 4 hour workshop, participants will be introduced to the new Formal "Design" Reuse methodology. Fundamentals of the Library Manager creation and verification process for Logical-Only and/or Logical-Physical Reuse Blocks for reusability in a corporate environment will be reviewed. We will also cover step-by-step procedures for instantiating Reuse Blocks into a Host project within DxDesigner, where layer mapping, bus definitions and global signal merging, can be user controlled. After instantiation, participants will learn how-to place and manipulate the physical reuse circuit within the Expedition PCB environment. Other items that will be reviewed include saving Source project constraints and how these CES rules merge with Host project constraints.  In addition, participants may be required to step through this same process during the lab portion of the session.

After this workshop, participants will be able to:

• Create, modify and verify a Logical-Only (L-O) and Logical-Physical (L-P) Reusable Circuit within Library Manager.
• Instantiate a saved verified L-O and L-P Reusable Circuit into a DxDesigner project, which includes multiple user controllable mapping/merging utilities.
• Be able to place and manipulate an L-P Reusable Layout Circuit within Expedition PCB. 

Advanced Packaging: Designing with Embedded Passives and Wirebonds
Tuesday, November 4, 2008 | 1:00pm - 5:00pm
Loy D'Souza, Technical Marketing Engineer, Mentor Graphics

In order to achieve better performance and yield with RF/Mixed technology designs it’s becoming more necessary to design with advanced packaging technologies. This workshop introduces two of the key technologies supported with Mentor Graphics PCB design tools: Embedded Passives as integral components fabricated into the board and hybrid design technologies of bonding bare dies on boards with wirebonds. 

The session includes hands on training on the following features:

• Embedded Materials and Embedded Manufacturing Process setup
• Planning designs to optimize EP designs for performance, cost and yield
• Techniques to easily incorporate changes in DFM parameters in PCB design
• Defining Bare Dies on PCB and Setting up Wirebond rules
• Automated Wirebonding patterns
• 3D DRC for Wirebonds and export to ACIS SAT

Drawing Editor
Tuesday, November 4, 2008 | 1:00pm - 5:00pm
Al Kilby, Technical Marketing Engineer, Mentor Graphics

PCB manufacturing documentation has been a requirement since the development of the technology. Having a drawing creation tool that is native to the Expedition environment presents advantages and capabilities that make documentation tasks easier for designers and detailers

This session will focus on basics such as:

• Template and drawing creation, and maintaining them in a library
• Creating and maintaining Variant data for Drawing Editor (and FabLink XE)
• Placement of boards (scaling, rotation, and matrices)
• Board based objects such as Drill charts and data, and Layer stackups
• Associative, Ordinate dimensioning, and GD&T dimensions and objects
• Multi-line text placement and editing
• Simple, and more detailed automation script examples for Drawing Editor
• Detail views
• Outputs (PDF and Extended Printing)

During this workshop participants will learn:

• An entry level understanding of the tools and capabilities of Drawing Editor in the Expedition Enterprise environment.

ECAD Collaboration across Multiple Organizations
Tuesday, November 4, 2008 | 1:00pm - 5:00pm
Matt Wuensch, Business Development Manager, Mentor Graphics

This workshop will teach attendees how to effectively collaborate ECAD designs throughout the design process, particularly on the Design-to-Manufacturing interface.  

During this workshop:

• Attendees will gain hands-on experience viewing, marking up and adding design review comments to a design—both at the schematic and layout phases.

HyperLynx 8.0
Tuesday, November 4, 2008 | 1:00pm - 5:00pm
Friday, November 7, 2008 | 1:00pm - 5:00pm
Steve McKinney, Technical Marketing Engineer, Mentor Graphics

This session covers how to run signal integrity simulations in HyperLynx® taking advantage of the new functionality to be introduced in HyperLynx 8.0.  The workshop will include both lecture and hands-on labs.

Topics covered will include:

• Attendees The new DDR2/3 Wizard, advanced integration features, selectable stimuli and simulation sweeps, and more.
• How to run signal integrity simulations in HyperLynx® taking advantage of the new functionality to be introduced in HyperLynx 8.0.

HyperLynx Thermal
Friday, November 7, 2008 | 1:00pm - 5:00pm
Patrick Carrier, Technical Marketing Engineer, Mentor Graphics

Users will get an overview of board-level thermal analysis using the new HyperLynx Thermal 9.0. Users will be introduced to new integration features of HyperLynx Thermal, as well as enhancements in analysis capabilities. Labs will go over exploring possible solutions to board-level thermal issues, and how they can be examined using HyperLynx Thermal. Workshop will include both lecture and hands-on labs.