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STARC recommends PowerPro’s clock gating For RTL Power Optimization

Success story

To aid its member companies in the design and development of LSI circuits, STARC (Semiconductor Technology Academic Research Center) develops and publishes reference flows. One of these, the RTL-to-layout STARCAD-CEL digital design flow, addresses the challenges of advanced process technologies below 65nm. Because power optimization is a central part of this flow, STARC is looking for new and effective ways to automate power optimization. Siemens EDA' PowerPro® CG and SLEC® Pro were evaluated and incorporated into version 2.0 of the STARCAD-CEL design flow. This paper discusses the evaluation criteria, process, and results that led to the certification of PowerPro by STARC for its member companies.

PowerPro to Optimize Power

STARC recommends using PowerPro to optimize power. The favorable results from this thorough evaluation show that PowerPro correctly and effectively identifies clock gating enable logic that reduces power. PowerPro increases productivity by inserting clock gating enable logic into the original RTL code such that the resulting optimized RTL is compatible and complementary to existing RTL design flows. PowerPro can be used on larger blocks, earlier in the design process to provide greater power savings and eliminate the effort spent on manual clock gating optimizations.

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