Tessent Advanced DFT
Tessent DefectSim
Tessent DefectSim is a transistor-level defect simulator for analog, mixed-signal (AMS), and non-scan digital circuits. It measures defect coverage and defect tolerance and is perfect for both high-volume and high-reliability ICs.
Why Tessent DefectSim?
Improve AMS Safety, Test Quality, and Time. Tessent DefectSim replaces manual test coverage assessment in AMS circuits, generating objective data to guide improvements needed to meet quality and functional safety standards and test coverage goals.
Analog fault simulation
Built on the transistor-level defect-injection techniques used in TestKompress Cell-Aware ATPG for scannable digital circuits, DefectSim is suitable for industrial circuit blocks containing hundreds or thousands of transistors.
Actionable output analysis
Generate an executive summary listing likelihood-weighted defect coverage, confidence interval, and a matrix listing each defect and whether it was detected by a failing test limit or a digital output.
Efficient simulation
Dramatically reduce total simulation time compared to simulating production tests and flat-extracted layout netlists in classic SPICE on parallel CPUs.
We evaluated Tessent DefectSim on several automotive ICs and concluded it is a highly-automated and flexible solution that guides improvements in test and design-for-test techniques and allows us to measurably improve the defect coverage of analog tests.
