Tessent Advanced DFT
Tessent Platform
Tessent Platform reduces DFT implementation effort with an optimal automation of the Tessent Shell flow for hierarchical DFT. This addresses the challenges of implementing hierarchical DFT by using intent-driven automation, universal test infrastructure, and future-proof customization.
Why Tessent Platform?
Tessent Platform helps IC design teams achieve manufacturing test quality goals faster and with fewer resources compared to traditional DFT methods. This production-proven automation enables a simple, consolidated hand-off between teams, resulting in a sustainable and predictable flow.
Faster DFT implementation
Define intent with specification-based IP insertion, a single, unified database, and Tessent Core Description based data transfer. DFT IP and Signals are automatically configured for all test modes.
Design compatibility
By leveraging IEEE 1687 (IJTAG) infrastructure, insertion, ICL extraction and PDL retargeting is supported for Tessent as well as third-party IP. Multiple chip-level interfaces are supported for manufacturing and in-system test.
Flexible use models
With integrated introspection and design editing customizations across the flow, the flow can be customized in a sustainable way. Custom DRCs, user-defined commands and custom pre- or post-insertion scripts can be utilized.
eSilicon uses Tessent Platform to help us meet our aggressive production schedules and deliver industry-leading ICs like those based on eSilicon’s neuASIC 7nm platform for machine learning.